公开(公告)号：US20120112540A1

公开(公告)日：2012-05-10

申请号：US13278755

申请日：2011-10-21

申请人： Hiromasa TAKEDA ,  Hiroki Fujisawa

发明人： Hiromasa TAKEDA ,  Hiroki Fujisawa

IPC分类号： H02J1/00

CPC分类号： H01L24/14 ,  G11C7/1057 ,  H01L23/49838 ,  H01L23/5286 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15311 ,  Y10T307/305 ,  Y10T307/50 ,  Y10T307/696 ,  Y10T307/707 ,  H01L2924/00

摘要： A semiconductor chip includes: a data output buffer that outputs a data signal; a first power-supply pad that supplies a first power-supply potential to the data output buffer; a power-supply wiring that is connected to the first power-supply pad; a strobe output buffer that outputs a strobe signal; and a second power-supply pad that supplies a second power-supply potential to the strobe output buffer. The power-supply wiring and the second power-supply pad are electrically independent of each other. Therefore, the power-supply noise associated with the switching of the data output buffer does not spread to the strobe output buffer. Thus, it is possible to improve the quality of the strobe signal.

摘要翻译： 半导体芯片包括：输出数据信号的数据输出缓冲器; 第一电源焊盘，其向所述数据输出缓冲器提供第一电源电位; 连接到所述第一电源焊盘的电源配线; 输出选通信号的选通输出缓冲器; 以及向所述选通输出缓冲器提供第二电源电位的第二电源焊盘。 电源布线和第二电源垫彼此电独立。 因此，与数据输出缓冲器的切换相关联的电源噪声不会扩展到选通输出缓冲器。 因此，可以提高选通信号的质量。

公开(公告)号：US08144524B2

公开(公告)日：2012-03-27

申请号：US12923254

申请日：2010-09-10

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

摘要： To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.

摘要翻译： 包括多个焊盘组，每个焊盘组包括在X方向上顺序布置的第一数据I / O焊盘，第一电源焊盘，第二数据I / O焊盘和第二电源焊盘。 第一数据I / O焊盘连接到第一数据I / O缓冲器，第二数据I / O焊盘连接到第二数据I / O缓冲器。 第一电源焊盘为第一和第二数据I / O缓冲器提供第一电源电位，第二电源焊盘向第一和第二数据I / O缓冲器提供第二电源电位。 包括在每个焊盘组中的第一数据I / O焊盘与包括在其它焊盘组中的第二电源焊盘或不包括在任何一个焊盘组中的多个电源焊盘中的任何一个电源焊盘相邻。

公开(公告)号：US07994812B2

公开(公告)日：2011-08-09

申请号：US12654253

申请日：2009-12-15

申请人： Fumiyuki Osanai ,  Hiroki Fujisawa

发明人： Fumiyuki Osanai ,  Hiroki Fujisawa

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.

摘要翻译： 调整输出缓冲器的阻抗水平的半导体器件包括复制缓冲电路，其包括与输出缓冲器基本相同的电路配置，计数器电路改变阻抗代码以改变副本缓冲器的阻抗电平;锁存电路暂时保持 响应于控制信号的阻抗代码，以及响应于从校准命令的发布而经过预定时间段而产生控制信号的终止确定电路，而不管复制缓冲器尚未达到期望的事实 阻抗水平。

公开(公告)号：US07923254B2

公开(公告)日：2011-04-12

申请号：US12310746

申请日：2007-09-05

申请人： Kusuki Nishioka ,  Tomohiro Kato ,  Hiroki Fujisawa

发明人： Kusuki Nishioka ,  Tomohiro Kato ,  Hiroki Fujisawa

IPC分类号： G01N33/48

CPC分类号： G01N33/5082

摘要： A method for studying, determining or evaluating a pharmacological action of a test substance, the method including subjecting the brain tissue of an SART stressed animal administered with the test substance to an expression proteome analysis, where expression changes of NSF (N-ethylmaleimide sensitive fusion protein), which is or is not modified after translation, in the SART stressed animal administered with the test substance as compared with an SART stressed animal to which a test substance is not administered is used as an index.

摘要翻译： 一种用于研究，确定或评估测试物质的药理学作用的方法，所述方法包括使施用受试物质的SART强调动物的脑组织进行表达蛋白质组分析，其中NSF（N-乙基马来酰亚胺敏感融合物）的表达变化 蛋白质）在翻译后进行或未被修饰的SART强调动物与被测物质相比未被施用测试物质的SART强调动物作为指标。

公开(公告)号：US20110063925A1

公开(公告)日：2011-03-17

申请号：US12923254

申请日：2010-09-10

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： G11C7/10 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2254

摘要： To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.

摘要翻译： 包括多个焊盘组，每个焊盘组包括在X方向上顺序布置的第一数据I / O焊盘，第一电源焊盘，第二数据I / O焊盘和第二电源焊盘。 第一数据I / O焊盘连接到第一数据I / O缓冲器，第二数据I / O焊盘连接到第二数据I / O缓冲器。 第一电源焊盘为第一和第二数据I / O缓冲器提供第一电源电位，第二电源焊盘向第一和第二数据I / O缓冲器提供第二电源电位。 包括在每个焊盘组中的第一数据I / O焊盘与包括在其它焊盘组中的第二电源焊盘或不包括在任何一个焊盘组中的多个电源焊盘中的任何一个电源焊盘相邻。

公开(公告)号：US07826305B2

公开(公告)日：2010-11-02

申请号：US12216675

申请日：2008-07-09

申请人： Hiroki Fujisawa

发明人： Hiroki Fujisawa

IPC分类号： G11C8/00

CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks LCLKE and LCLKO. Thus, the counting of the latency is performed based not on the internal clock LCLK itself but on the divided clocks LCLKE and LCLKO obtained by frequency-dividing the internal clock LCLK. Thus, even when a frequency of the internal clock LCLK is high, an operation margin can be sufficiently secured.

摘要翻译： 延迟计数器包括：分频电路，其基于内部时钟LCLK产生相位彼此相对的多个分频时钟LCLKE和LCLKO; 以及分频计数器电路，每个计数器电路根据对应的分频时钟LCLKE和LCLKO计数内部命令的等待时间。 因此，等待时间的计数不是基于内部时钟LCLK本身而是通过对内部时钟LCLK进行分频而获得的分频时钟LCLKE和LCLKO进行的。 因此，即使当内部时钟LCLK的频率高时，也可以充分确保操作余量。

公开(公告)号：US07755953B2

公开(公告)日：2010-07-13

申请号：US11895695

申请日：2007-08-27

申请人： Hiroki Fujisawa

发明人： Hiroki Fujisawa

IPC分类号： G11C7/10

CPC分类号： G11C8/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1087 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4093 ,  G11C2207/107

摘要： A semiconductor memory device includes an FIFO block connected to a data input/output terminal DQ, a time-division transfer circuit that inputs and outputs in parallel n-bit data inputted and outputted continuously via the data input/output terminal DQ, a data bus RWBS that performs a data transfer between the time-division transfer circuit and the FIFO block, and a mode register that sets a burst length. When a minimum burst length settable to the mode register is m (

摘要翻译： 半导体存储器件包括连接到数据输入/输出端子DQ的FIFO块，并行地输入和输出通过数据输入/输出端子DQ输入和输出的n位数据的时分传输电路，数据总线 执行时分传输电路和FIFO块之间的数据传输的RWBS以及设置突发长度的模式寄存器。 当设置到模式寄存器的最小突发长度为m（

公开(公告)号：US07688671B2

公开(公告)日：2010-03-30

申请号：US11582981

申请日：2006-10-19

申请人： Yuki Hosoe ,  Hiroki Fujisawa

发明人： Yuki Hosoe ,  Hiroki Fujisawa

IPC分类号： G11C8/00 ,  G11C5/14

CPC分类号： H03L7/0812 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory chip with an On-Die Termination (ODT) function is disclosed, which comprises a delay locked loop (DLL) circuit, a synchronous circuit, an asynchronous circuit, a select signal generator, and a selector. The DLL circuit is configured to produce a local clock signal in response to a clock signal when a clock enable (CKE) signal is asserted. The DLL circuit has a predetermined boost time. The select signal generator is configured to assert a select signal in consideration of the predetermined boost time. The selector is configured to select an output of the asynchronous circuit until the select signal is asserted but to select another output of the synchronous circuit after the select signal is asserted.

摘要翻译： 公开了一种具有片上终端（ODT）功能的半导体存储器芯片，其包括延迟锁定环（DLL）电路，同步电路，异步电路，选择信号发生器和选择器。 DLL电路被配置为当时钟使能（CKE）信号被断言时响应于时钟信号产生本地时钟信号。 DLL电路具有预定的升压时间。 选择信号发生器被配置为考虑到预定的提升时间来确定选择信号。 选择器被配置为选择异步电路的输出，直到选择信号被断言，但是在选择信号被置位之后选择同步电路的另一个输出。

公开(公告)号：US20090289659A1

公开(公告)日：2009-11-26

申请号：US12453730

申请日：2009-05-20

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/028

摘要： In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.

摘要翻译： 在校准控制电路中，第一时钟门电路在校准周期期间限制参考更新时钟的通过，以停止参考更新时钟中的第一个，并将限制参考更新时钟作为第一更新时钟CLK1提供给命中确定 电路和第二时钟门电路。 第二时钟门电路110通过第一更新时钟CLK1直到从命中确定电路接收到命中信号，并将第二更新时钟CLK2递送到升/降计数器106.升/减计数器106由第二更新 时钟CLK2。 利用这种结构，在校准期间可以增加用于调整步骤的第二更新时钟的数量。

公开(公告)号：US20090272649A1

公开(公告)日：2009-11-05

申请号：US12310746

申请日：2007-09-05

申请人： Kusuki Nishioka ,  Tomohiro Kato ,  Hiroki Fujisawa

发明人： Kusuki Nishioka ,  Tomohiro Kato ,  Hiroki Fujisawa

IPC分类号： G01N27/447 ,  C12Q1/68 ,  C12Q1/70

CPC分类号： G01N33/5082

摘要： A method for studying, determining or evaluating a pharmacological action of a test substance, the method including subjecting the brain tissue of an SART stressed animal administered with the test substance to an expression proteome analysis, where expression changes of NSF (N-ethylmaleimide sensitive fusion protein), which is or is not modified after translation, in the SART stressed animal administered with the test substance as compared with an SART stressed animal to which a test substance is not administered is used as an index.

摘要翻译： 一种用于研究，确定或评估测试物质的药理学作用的方法，所述方法包括使施用受试物质的SART强调动物的脑组织进行表达蛋白质组分析，其中NSF（N-乙基马来酰亚胺敏感融合物）的表达变化 蛋白质）在翻译后进行或未被修饰的SART强调动物与被测物质相比未被施用测试物质的SART强调动物作为指标。