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    Semiconductor memory device and manufacturing method thereof
    22.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09171886B2

    公开(公告)日：2015-10-27

    申请号：US13032359

    申请日：2011-02-22

    申请人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

    发明人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

    IPC分类号： H01L29/82 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12

    CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L43/12

    摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

    摘要翻译： 根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。 接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。 存储元件设置在接触插头的上表面上并存储数据。 在存储元件上提供布线。

    Semiconductor storage device and method of manufacturing the same
    23.
    发明授权
    Semiconductor storage device and method of manufacturing the same 有权
    半导体存储装置及其制造方法

    公开(公告)号：US08786038B2

    公开(公告)日：2014-07-22

    申请号：US13230746

    申请日：2011-09-12

    申请人： Keiji Hosotani ,  Hiroyuki Kanaya

    发明人： Keiji Hosotani ,  Hiroyuki Kanaya

    IPC分类号： H01L29/82 ,  H01L21/00

    CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

    摘要： A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.

    摘要翻译： 根据本实施例的半导体存储装置包括形成在半导体衬底的表面上的选择元件。 下电极连接到选择元件。 在下电极上设置磁性隧道结元件。 上部电极设置在磁性隧道结元件上。 生长层设置在上电极上并由导电材料构成，并且当从半导体衬底的表面上方观察时具有比上电极大的面积。 在生长层上设置布线。

    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    24.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20110266600A1

    公开(公告)日：2011-11-03

    申请号：US13032359

    申请日：2011-02-22

    申请人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

    发明人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

    IPC分类号： H01L29/82 ,  H01L21/8246

    CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L43/12

    摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

    摘要翻译： 根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。 接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。 存储元件设置在接触插头的上表面上并存储数据。 在存储元件上设置接线。

    Semiconductor apparatus and method for manufacturing the semiconductor apparatus
    25.
    发明授权
    Semiconductor apparatus and method for manufacturing the semiconductor apparatus 失效
    半导体装置及半导体装置的制造方法

    公开(公告)号：US07750383B2

    公开(公告)日：2010-07-06

    申请号：US11858361

    申请日：2007-09-20

    申请人： Hiroyuki Kanaya

    发明人： Hiroyuki Kanaya

    IPC分类号： H01L27/108

    CPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/11502 ,  H01L28/56

    摘要： According to an aspect of the present invention, there is provided a semiconductor apparatus including a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulating film disposed on the semiconductor substrate, a ferroelectric capacitor and an upper mask. The ferroelectric capacitor includes a lower electrode disposed on the insulating film, a ferroelectric film disposed on the lower electrode and an upper electrode disposed on the ferroelectric film. The upper mask includes a hard mask disposed on the upper electrode and a sidewall mask disposed on at least part of a sidewall of the hard mask.

    摘要翻译： 根据本发明的一个方面，提供一种包括半导体衬底，形成在半导体衬底上的晶体管，设置在半导体衬底上的绝缘膜，铁电电容器和上掩模的半导体器件。 铁电电容器包括设置在绝缘膜上的下电极，设置在下电极上的铁电体膜和设置在铁电体膜上的上电极。 上掩模包括设置在上电极上的硬掩模和设置在硬掩模的侧壁的至少一部分上的侧壁掩模。

    Ferroelectric memory device and method of manufacturing the same
    26.
    发明授权
    Ferroelectric memory device and method of manufacturing the same 失效
    铁电存储器件及其制造方法

    公开(公告)号：US07700987B2

    公开(公告)日：2010-04-20

    申请号：US11276781

    申请日：2006-03-14

    申请人： Hiroyuki Kanaya

    发明人： Hiroyuki Kanaya

    IPC分类号： H01L27/108

    CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

    摘要： A ferroelectric memory device includes a top electrode, a bottom electrode, a ferroelectric film which is sandwiched between the top and bottom electrodes, includes a first portion having a side surface flushed with a side surface of the top electrode and a second portion having a side surface flushed with a side surface of the bottom electrode, and has a step formed by making the side surface of the second portion project outward from the side surface of the first portion, a top mask which is provided on the top electrode, and a side mask which is provided on part of a side surface of the top mask, the side surfaces of the top electrode and the first portion of the ferroelectric film and has a top at a lower level than a top of the top mask and at a higher level than a top of the top electrode.

    摘要翻译： 铁电存储器件包括顶电极，底电极，夹在顶电极和底电极之间的铁电膜，包括具有用顶电极的侧表面冲洗的侧表面的第一部分和具有侧面的第二部分 表面用底部电极的侧表面冲洗，并且具有通过使第二部分的侧表面从第一部分的侧表面向外突出，设置在顶部电极上的顶部掩模和侧面 掩模，其设置在顶部掩模的侧表面的一部分，顶部电极的侧表面和铁电体膜的第一部分上，并且具有比顶部掩模的顶部更低的顶部和更高的水平面 比顶部电极的顶部。

    Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method
    29.
    发明授权
    Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
    通过该方法形成FeRAM电容器和FeRAM电容器的制造方法

    公开(公告)号：US07001780B2

    公开(公告)日：2006-02-21

    申请号：US10635140

    申请日：2003-08-06

    申请人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

    发明人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

    IPC分类号： H01L21/00

    CPC分类号： H01L28/86 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

    摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

    摘要翻译： 铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。 底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的阻挡元件隔开。 阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。 这意味着在底电极的蚀刻期间不形成Ir栅栏。 此外，很少的Ir和/或IrO 2 <2>通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料的风险。