公开(公告)号：US09171886B2

公开(公告)日：2015-10-27

申请号：US13032359

申请日：2011-02-22

申请人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

发明人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

IPC分类号： H01L29/82 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L43/12

摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

摘要翻译： 根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。 接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。 存储元件设置在接触插头的上表面上并存储数据。 在存储元件上提供布线。

公开(公告)号：US20110266600A1

公开(公告)日：2011-11-03

申请号：US13032359

申请日：2011-02-22

申请人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

发明人： Hiroyuki Kanaya ,  Yukinori Koyama ,  Susumu Shuto ,  Kuniaki Sugiura

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L27/228 ,  H01L21/76897 ,  H01L43/12

摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

摘要翻译： 根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。 在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。 接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。 存储元件设置在接触插头的上表面上并存储数据。 在存储元件上设置接线。

公开(公告)号：US06190957B1

公开(公告)日：2001-02-20

申请号：US09324501

申请日：1999-06-02

申请人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

发明人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

IPC分类号： H01L218242

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L27/10852 ,  H01L27/11502 ,  H01L28/55

摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成 在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线 电容器接触插头。

公开(公告)号：US5990507A

公开(公告)日：1999-11-23

申请号：US889470

申请日：1997-07-08

申请人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

发明人： Hiroshi Mochizuki ,  Kumi Okuwada ,  Hiroyuki Kanaya ,  Osamu Hidaka ,  Susumu Shuto ,  Iwao Kunishima

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L27/10852 ,  H01L27/11502 ,  H01L28/55

摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成 在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线 电容器接触插头。

公开(公告)号：US09276195B2

公开(公告)日：2016-03-01

申请号：US13965149

申请日：2013-08-12

申请人： Hiroyuki Kanaya ,  Kuniaki Sugiura

发明人： Hiroyuki Kanaya ,  Kuniaki Sugiura

IPC分类号： H01L29/82 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L43/08

摘要： According to one embodiment, a magnetic random access memory includes a magnetoresistive element, a contact arranged under the magnetoresistive element and connected to the magnetoresistive element, and an insulating film continuously formed from a periphery of the contact to a side surface of the magnetoresistive element and including a protective portion covering the side surface of the magnetoresistive element.

摘要翻译： 根据一个实施例，磁性随机存取存储器包括磁阻元件，布置在磁阻元件下方并连接到磁阻元件的触点，以及从触点的周边连续形成到磁阻元件的侧表面的绝缘膜，以及 包括覆盖磁阻元件的侧表面的保护部分。

公开(公告)号：US08786038B2

公开(公告)日：2014-07-22

申请号：US13230746

申请日：2011-09-12

申请人： Keiji Hosotani ,  Hiroyuki Kanaya

发明人： Keiji Hosotani ,  Hiroyuki Kanaya

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.

摘要翻译： 根据本实施例的半导体存储装置包括形成在半导体衬底的表面上的选择元件。 下电极连接到选择元件。 在下电极上设置磁性隧道结元件。 上部电极设置在磁性隧道结元件上。 生长层设置在上电极上并由导电材料构成，并且当从半导体衬底的表面上方观察时具有比上电极大的面积。 在生长层上设置布线。

公开(公告)号：US07750383B2

公开(公告)日：2010-07-06

申请号：US11858361

申请日：2007-09-20

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L27/108

CPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/11502 ,  H01L28/56

摘要： According to an aspect of the present invention, there is provided a semiconductor apparatus including a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulating film disposed on the semiconductor substrate, a ferroelectric capacitor and an upper mask. The ferroelectric capacitor includes a lower electrode disposed on the insulating film, a ferroelectric film disposed on the lower electrode and an upper electrode disposed on the ferroelectric film. The upper mask includes a hard mask disposed on the upper electrode and a sidewall mask disposed on at least part of a sidewall of the hard mask.

摘要翻译： 根据本发明的一个方面，提供一种包括半导体衬底，形成在半导体衬底上的晶体管，设置在半导体衬底上的绝缘膜，铁电电容器和上掩模的半导体器件。 铁电电容器包括设置在绝缘膜上的下电极，设置在下电极上的铁电体膜和设置在铁电体膜上的上电极。 上掩模包括设置在上电极上的硬掩模和设置在硬掩模的侧壁的至少一部分上的侧壁掩模。

公开(公告)号：US07700987B2

公开(公告)日：2010-04-20

申请号：US11276781

申请日：2006-03-14

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L27/108

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

摘要： A ferroelectric memory device includes a top electrode, a bottom electrode, a ferroelectric film which is sandwiched between the top and bottom electrodes, includes a first portion having a side surface flushed with a side surface of the top electrode and a second portion having a side surface flushed with a side surface of the bottom electrode, and has a step formed by making the side surface of the second portion project outward from the side surface of the first portion, a top mask which is provided on the top electrode, and a side mask which is provided on part of a side surface of the top mask, the side surfaces of the top electrode and the first portion of the ferroelectric film and has a top at a lower level than a top of the top mask and at a higher level than a top of the top electrode.

摘要翻译： 铁电存储器件包括顶电极，底电极，夹在顶电极和底电极之间的铁电膜，包括具有用顶电极的侧表面冲洗的侧表面的第一部分和具有侧面的第二部分 表面用底部电极的侧表面冲洗，并且具有通过使第二部分的侧表面从第一部分的侧表面向外突出，设置在顶部电极上的顶部掩模和侧面 掩模，其设置在顶部掩模的侧表面的一部分，顶部电极的侧表面和铁电体膜的第一部分上，并且具有比顶部掩模的顶部更低的顶部和更高的水平面 比顶部电极的顶部。

公开(公告)号：US07531408B2

公开(公告)日：2009-05-12

申请号：US11754022

申请日：2007-05-25

申请人： Keisuke Nakazawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Soichi Yamazaki ,  Hiroshi Itokawa ,  Hiroyuki Kanaya

发明人： Keisuke Nakazawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Soichi Yamazaki ,  Hiroshi Itokawa ,  Hiroyuki Kanaya

IPC分类号： H01L21/8234

CPC分类号： H01L27/11502 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

摘要： A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.

摘要翻译： 一种半导体器件的制造方法，包括在半导体衬底上形成电容器，所述电容器包括含有Pb，Zr，Ti和O的电介质膜。形成所述电容器包括形成含有Pb，Sr，Zr，Ti， 汝和O.

公开(公告)号：US20090095994A1

公开(公告)日：2009-04-16

申请号：US12250888

申请日：2008-10-14

申请人： Hiroyuki Kanaya ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Yoshinori Kumura

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/44

CPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/105 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/65

摘要： A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode.

摘要翻译： 半导体器件包括衬底; 形成在所述基板上的绝缘层; 穿过所述绝缘层形成的接触孔; 多个第一插头电极，每个第一插头电极各自形成在所述接触孔内部到所述绝缘层的表面; 在第一区域中形成在所述第一插头电极上的电容器层; 以及形成在与第一区域不同的第二区域中的第一插塞电极上的第二插头电极。 电容器层包括下电极，铁电体膜和依次堆叠的上电极。 第一插头电极包括从基板的表面形成的插头导电层和从插塞导电层的上方形成的插塞阻挡层，直到绝缘层的上表面，插塞阻挡层具有比 下电极。