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公开(公告)号：US20190155330A1
公开(公告)日：2019-05-23
申请号：US15754614
申请日：2015-08-24
Applicant: HITACHI, LTD.
Inventor： Masanao YAMAOKA , Takeshi KATO , Chihiro YOSHIMURA , Masato HAYASHI
Abstract: An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer.
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公开(公告)号：US20160064050A1
公开(公告)日：2016-03-03
申请号：US14642047
申请日：2015-03-09
Applicant: Hitachi, Ltd.
Inventor： Chihiro YOSHIMURA , Masanao YAMAOKA
CPC classification number: G11C7/12 , G06N7/005 , G06N99/002 , G11C5/02 , G11C5/147 , G11C8/08 , G11C8/10 , G11C11/412 , G11C11/419
Abstract: A semiconductor device includes a spin array in which a plurality of memory cells are disposed in a matrix configuration, a group of a predetermined number of memory cells is collected in units of spin units, and a plurality of the spin units are disposed with an adjacency; a word line provided in correspondence with rows of the memory cells; a bit line pair provided in correspondence with columns of the memory cells; a multiword decoder configured to multiplex a word address according to an input of a multiplicity specify signal to a word line and simultaneously activate a plurality of word lines; and a bit line driver configured to subject a plurality of memory cells, of the memory cells connected to bit line pairs and arrayed in a column direction, activated by the plurality of the word lines to a write operation or a read operation.
Abstract translation: 半导体器件包括其中多个存储单元以矩阵配置布置的自旋阵列，以自旋单元为单位收集预定数量的存储单元的组，并且多个自旋单元以邻接 ; 与存储单元的行对应地设置的字线; 与存储器单元的列相对应地提供的位线对; 多字解码器，被配置为根据多重指定信号的输入将字地址复用到字线并同时激活多个字线; 以及位线驱动器，其被配置为使由多个字线激活的存储单元连接到位线对并排列在列方向上的多个存储器单元进行写操作或读操作。
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公开(公告)号：US20220308837A1
公开(公告)日：2022-09-29
申请号：US17399091
申请日：2021-08-11
Applicant: Hitachi, Ltd.
Inventor： Yusuke SUGITA , Takuya OKUYAMA , Masanao YAMAOKA
Abstract: Provided is an optimization method including executing a ground state search for an interaction model by a ground state search in a surrogate interaction model including D (D is a natural number of three or more) variable groups each having N continuous variables by using an information processing apparatus, the interaction model having a third-order or higher-order energy function including N (N is a natural number) continuous variables and discrete variables. The ground state search is executed based on simulated annealing. An interaction relation of the surrogate interaction model has a complete D-part graph structure. A coupling is set between i-th variable pairs in the respective variable groups of the surrogate interaction model. The information processing apparatus is operated to simultaneously update all variables of one variable group from among the D variable groups when performing a state transition in the surrogate interaction model.
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24.发明申请公开(公告)号：US20220027082A1
公开(公告)日：2022-01-27
申请号：US17274449
申请日：2020-04-29
Applicant: Hitachi, Ltd.
Inventor： Takuya OKUYAMA , Masanao YAMAOKA
Abstract: A calculation system includes a variable memory storing a value indicating a state of a variable of a mixed integer quadratic programming problem; a state transition calculation block that calculates the next state of the value indicating the state of the variable; a nonlinear coefficient memory that stores a nonlinear coefficient of the state transition calculation block; a linear coefficient memory that stores a linear coefficient of the state transition calculation block; a weight input line that receives a weight signal of the state transition calculation block; and a temperature input line that receives a temperature signal of the state transition calculation block. The state transition calculation block includes a difference calculation block that calculates a difference calculation by using the weight signal, the nonlinear coefficient, and the linear coefficient. A next state determination block calculates the next state of the variable using the value read from the variable memory.
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Patent Agency Ranking
公开(公告)号：US20210398156A1
公开(公告)日：2021-12-23
申请号：US17289473
申请日：2019-10-25
Applicant: HITACHI, LTD.
Inventor： Jun OGAWA , Yukiyo KIMURA , Takuya OKUYAMA , Masanao YAMAOKA
Abstract: An information providing device 100 is configured to include a storage unit 101 that stores price information 125 on various financial products, and a calculation unit 104 that performs calculation on an Ising model in which a price increase-decrease event of each financial product on an estimated price determined based on an actual price of the financial product indicated in the price information and a sensitivity of the financial product to another financial product is set as a spin, and in which sensitivities between prices of the financial products are set as the strengths of interactions between the spins, wherein the calculation unit outputs, to a specified device, information on a future price of at least one financial product of the financial products based on a result of the calculation.
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公开(公告)号：US20170185380A1
公开(公告)日：2017-06-29
申请号：US15324178
申请日：2014-07-09
Applicant: HITACHI, LTD.
Inventor： Masato HAYASHI , Masanao YAMAOKA , Chihiro YOSHIMURA
CPC classification number: G06F7/588 , G06F17/18 , G06N7/005 , G06N99/002 , G11C11/16 , H01L27/11 , H03L7/26
Abstract: A spin unit provided with a memory cell that stores a value of one spin of an Ising model, a memory cell that stores an interaction coefficient from an adjacent spin which interacts with the corresponding spin, a memory cell that stores an external magnetic field coefficient of the one spin and circuits that determine the next state of the one spin on the basis of a product of a value of each adjacent spin and the corresponding interaction coefficient and the external magnetic field coefficient is configured, the semiconductor device is provided with a spin array where the plural spin units are arranged and connected on a two-dimensional plane on a semiconductor substrate, a random number generator and a bit regulator, the bit regulator operates output of the random number generator and supplies a random bit to all spin units in the spin array via one wire.
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公开(公告)号：US20160065210A1
公开(公告)日：2016-03-03
申请号：US14638205
申请日：2015-03-04
Applicant: HITACHI, LTD.
Inventor： Chihiro YOSHIMURA , Masanao YAMAOKA , Masato HAYASHI
IPC: H03K19/00
CPC classification number: H03K19/0002 , G06N7/005 , G06N99/005 , G11C11/1659 , G11C11/5607
Abstract: An object of the present invention is to realize an example of configuration that approximately represents a state of quantum spin in a semiconductor device where components as a basic configuration unit are arrayed so as to search a ground state of Ising model. There is disclosed a semiconductor device provided with plural units each of which is equipped with a first memory cell that stores a value which represents one spin of the Ising model by three or more states, a second memory cell that stores an interaction coefficient showing interaction from another spin which exerts interaction on the one spin and a logical circuit that determines the next state of the one spin on the basis of a function having a value which represents a state of the other spin and the interaction coefficient as a constant or a variable.
Abstract translation: 本发明的目的是实现一种近似表示半导体装置中的量子自旋状态的配置示例，其中将作为基本配置单元的组件排列以搜索Ising模型的基态。 公开了一种设置有多个单元的半导体器件，每个单元配备有第一存储器单元，其存储表示Ising模型的一个自旋的值由三个或更多个状态，第二存储单元，其存储显示相互作用的相互作用系数 基于具有表示另一个自旋的状态的值的函数和作为常数或变量的相互作用系数的函数确定一个自旋的下一个状态的逻辑电路的另一自旋在一个自旋上发生相互作用。
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公开(公告)号：US20160064080A1
公开(公告)日：2016-03-03
申请号：US14642266
申请日：2015-03-09
Applicant: HITACHI, LTD.
Inventor： Masanao YAMAOKA , Takashi OSHIMA , Masato HAYASHI
CPC classification number: G06F13/1668 , G06F13/1652 , G06N7/005 , G06N99/002 , G11C5/08 , G11C7/1006 , G11C11/16 , G11C14/0081 , G11C2213/71
Abstract: In a semiconductor device which calculates an interaction model, a technique capable of executing interaction calculation in non-synchronization with a clock is provided. The semiconductor device includes a plurality of units each of which includes: a first memory cell for storing a value indicating a state of one node of an interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node; and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient.
Abstract translation: 在计算交互模型的半导体装置中，提供能够执行与时钟不同步的交互计算的技术。 半导体器件包括多个单元，每个单元包括：第一存储器单元，用于存储指示交互模型的一个节点的状态的值; 第二存储器单元，用于存储指示来自连接到所述一个节点的节点的交互的交互系数; 以及交互计算电路，用于基于由指示所述连接节点的状态的值和所述交互系数确定的电流来确定指示所述一个节点的下一状态的值。
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公开(公告)号：US20150156569A1
公开(公告)日：2015-06-04
申请号：US14558802
申请日：2014-12-03
Applicant: Hitachi, Ltd.
Inventor： Kenichi TANAKA , Yong LEE , Masanao YAMAOKA
IPC: H04Q11/00 , H04B10/275 , H04B10/25
CPC classification number: H04Q11/0005 , H04B10/032 , H04B10/275 , H04J14/0283 , H04Q11/0062 , H04Q2011/0043 , H04Q2011/0052 , H04Q2011/0081 , H04Q2011/0083 , H04Q2011/0096
Abstract: In an optical transmission system including at least one ring network configured by plural nodes, each node of the ring network is provided with the optical switch having connection configuration that the output in at least two directions of a signal input to the node is allowed and the output of the optical switch functions as input to another node included in the plural nodes.
Abstract translation: 在包括由多个节点配置的至少一个环形网络的光传输系统中，环形网络的每个节点设置有具有连接配置的光开关，使得输入到节点的信号的至少两个方向上的输出被允许， 光开关的输出作为输入到多个节点中包括的另一个节点。
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