公开(公告)号：US09478611B2

公开(公告)日：2016-10-25

申请号：US14715041

申请日：2015-05-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786 ,  H01L29/04 ,  H01L29/20 ,  H01L29/34 ,  H01L21/02 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/41

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02538 ,  H01L21/02603 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/34 ,  H01L29/413 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/78681

Abstract: An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

Abstract translation: 示例性半导体结构包括第一表面和至少一个纳米线，所述至少一个纳米线垂直于所述第一表面，其中所述第一表面是缺陷差的并且由掺杂的III-V半导体材料制成，其中所述至少一个 一个纳米线是缺陷缺陷的，并且由与第一表面的材料具有约0％至1％的晶格失配的未掺杂的III-V半导体材料制成。

公开(公告)号：US20160240532A1

公开(公告)日：2016-08-18

申请号：US15138056

申请日：2016-04-25

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L27/088 ,  H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

公开(公告)号：US09324818B2

公开(公告)日：2016-04-26

申请号：US14671134

申请日：2015-03-27

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及栅极全能半导体器件及其制造方法。 一方面，该方法包括在STI区域之间的半导体衬底上提供由源区域和漏极区域锚定的至少一个悬浮纳米结构。 悬浮的纳米结构由与半导体衬底的结晶半导体材料不同的结晶半导体材料形成。 一个栅极叠层围绕至少一个悬浮的纳米结构。