公开(公告)号：US20230170393A1

公开(公告)日：2023-06-01

申请号：US17921781

申请日：2021-04-28

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/7786

Abstract: A Group III nitride-based transistor device is provided that has a gate drain capacitance (CGD), a drain source capacitance (CDS) and a drain source on resistance (RDSon). A ratio of the gate drain capacitance (CGD) at a drain source voltage (VDS) of 0V, CGD (0V), and the gate drain capacitance CGD at a value of VDS>0V, CGDV, is at least 3:1, wherein VDS is less than 15V.

公开(公告)号：US20230155000A1

公开(公告)日：2023-05-18

申请号：US18093434

申请日：2023-01-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/0217 ,  H01L21/268 ,  H01L21/26546 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/205 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/41725

Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.

公开(公告)号：US20210336015A1

公开(公告)日：2021-10-28

申请号：US17228973

申请日：2021-04-13

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/765 ,  H01L29/66

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

公开(公告)号：US11031327B2

公开(公告)日：2021-06-08

申请号：US15981662

申请日：2018-05-16

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner

IPC: H01L23/498 ,  H01L23/48 ,  H01L29/417 ,  H01L29/73 ,  H01L29/08 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/12

Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.

公开(公告)号：US10665531B2

公开(公告)日：2020-05-26

申请号：US16272545

申请日：2019-02-11

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L21/768

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a lateral transistor arranged in the front surface of the semiconductor substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines side walls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source of the lateral transistor.

公开(公告)号：US10410956B2

公开(公告)日：2019-09-10

申请号：US15192283

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L23/532 ,  H01L29/78 ,  H01L29/417 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L21/288 ,  H01L21/768 ,  H01L23/528

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the semiconductor substrate, a conductive plug filling a first portion of the via and a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug.

公开(公告)号：US10074721B2

公开(公告)日：2018-09-11

申请号：US15273231

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Simone Lavanga

IPC: H01L21/304 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: In an embodiment, a method of planarizing a surface includes applying a first layer to a surface including a protruding region such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface.

公开(公告)号：US20180158941A1

公开(公告)日：2018-06-07

申请号：US15370639

申请日：2016-12-06

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L29/20 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7786

Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride based transistor arranged on a front surface of the substrate, and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the substrate, and conductive material extending from the front surface to the rear surface of the substrate. The via tapers from the front surface to the rear surface of the substrate.

公开(公告)号：US09929107B1

公开(公告)日：2018-03-27

申请号：US15370536

申请日：2016-12-06

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L21/00 ,  H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L23/48 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L23/562 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7786 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/351

Abstract: In an embodiment, a method includes forming an opening in a front surface of a substrate including at least one Group III nitride-based transistor on the first surface, inserting conductive material into the opening, and coupling a source electrode of the Group III nitride-based transistor to a rear surface of the substrate with the conductive material.

公开(公告)号：US20180083107A1

公开(公告)日：2018-03-22

申请号：US15273231

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Simone Lavanga

IPC: H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: In an embodiment, a method of planarising a surface includes applying a first layer to a surface including a protruding region such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface.