公开(公告)号：US20190227963A1

公开(公告)日：2019-07-25

申请号：US16368688

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： George Chong Hean Ooi ,  Lai Guan Tang ,  Chee Hak Teh

IPC: G06F13/20 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  G06F17/50 ,  H04L12/861

Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

公开(公告)号：US20190197006A1

公开(公告)日：2019-06-27

申请号：US15853005

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Chee Hak Teh

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4239 ,  G06F13/1673 ,  G06F13/4059 ,  G06F13/4282

Abstract: Systems and methods for an interface with a widened interface-to-fabric shoreline between semiconductor circuits and a narrower interface-to-memory controller shoreline. The interface providing transitions from a first clock of a first circuit (e.g., field-programmable gate array (FPGA)), a second clock of a second circuit (e.g., high-bandwidth memory generation 2 (HBM2) stack, and a third clock of a physical layer of the second circuit. A first transfer between the first clock and the second clock may use a first set of first-in first-outs (FIFO) buffers, such as rate-matching FIFO buffers. A second transfer between the second clock and the third clock may use a second set of FIFO buffers, such as phase compensation FIFOs.

公开(公告)号：US11714941B2

公开(公告)日：2023-08-01

申请号：US17392218

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  Md Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

CPC classification number: G06F30/34 ,  G06F15/7825 ,  H03K19/17744 ,  H03K19/17796 ,  H04L12/43

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US20230049681A1

公开(公告)日：2023-02-16

申请号：US17973428

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

IPC: G06F1/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

公开(公告)号：US20220197855A1

公开(公告)日：2022-06-23

申请号：US17132663

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ilya K. Ganusov ,  Ashish Gupta ,  Chee Hak Teh ,  Sean R. Atsatt ,  Scott Jeremy Weber ,  Parivallal Kannan ,  Aman Gupta ,  Gary Brian Wallichs

IPC: G06F15/78 ,  H04L12/933 ,  H04L12/773

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

公开(公告)号：US11301412B2

公开(公告)日：2022-04-12

申请号：US15853005

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Chee Hak Teh

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

Abstract: Systems and methods for an interface with a widened interface-to-fabric shoreline between semiconductor circuits and a narrower interface-to-memory controller shoreline. The interface providing transitions from a first clock of a first circuit (e.g., field-programmable gate array (FPGA)), a second clock of a second circuit (e.g., high-bandwidth memory generation 2 (HBM2) stack, and a third clock of a physical layer of the second circuit. A first transfer between the first clock and the second clock may use a first set of first-in first-outs (FIFO) buffers, such as rate-matching FIFO buffers. A second transfer between the second clock and the third clock may use a second set of FIFO buffers, such as phase compensation FIFOs.

公开(公告)号：US20220014200A1

公开(公告)日：2022-01-13

申请号：US17181973

申请日：2021-02-22

Applicant: Intel Corporation

Inventor： Chang Kian Tan ,  Chee Hak Teh

IPC: H03K19/17736 ,  G06F11/10 ,  H03K19/1776 ,  G11C11/419 ,  G11C11/418 ,  G11C29/52 ,  G11C7/10

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.

公开(公告)号：US20210303491A1

公开(公告)日：2021-09-30

申请号：US17347324

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： George Chong Hean Ooi ,  Lai Guan Tang ,  Chee Hak Teh

IPC: G06F13/20 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H04L12/861 ,  G06F30/34

Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

公开(公告)号：US20210072908A1

公开(公告)日：2021-03-11

申请号：US16953138

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Curtis Wortman ,  Jeffrey Erik Schulz

IPC: G06F3/06 ,  G11C7/10 ,  G06F13/38

Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.

公开(公告)号：US10931283B2

公开(公告)日：2021-02-23

申请号：US16351268

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Chang Kian Tan ,  Chee Hak Teh

IPC: H03K19/17 ,  H03K19/17736 ,  G06F11/10 ,  H03K19/1776 ,  G11C11/419 ,  G11C11/418 ,  G11C29/52 ,  G11C7/10 ,  G11C8/06 ,  G11C29/04

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.