公开(公告)号：US09262347B2

公开(公告)日：2016-02-16

申请号：US14126926

申请日：2013-10-30

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

IPC: H04B17/00 ,  G06F13/00

CPC classification number: G06F13/4282 ,  G06F1/14 ,  G06F13/00 ,  G06F13/385 ,  H04L43/0858 ,  H04L43/106

Abstract: In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。

公开(公告)号：US11675003B2

公开(公告)日：2023-06-13

申请号：US16725954

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Daniel S. Froelich ,  Debendra Das Sharma

IPC: G01R31/317 ,  G06F11/22 ,  H04B3/46 ,  G01R31/3177 ,  G01R31/28 ,  G01R31/327 ,  G06F11/00 ,  G06F11/07 ,  G06F11/36 ,  G06F13/16 ,  H01L21/66

CPC classification number: G01R31/31703 ,  G01R31/3177 ,  G01R31/31725 ,  G06F11/221 ,  H04B3/46 ,  G01R31/2851 ,  G01R31/3275 ,  G06F11/00 ,  G06F11/0751 ,  G06F11/2205 ,  G06F11/3688 ,  G06F13/1689 ,  H01L22/34 ,  H01L2225/06596

Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

公开(公告)号：US20210081288A1

公开(公告)日：2021-03-18

申请号：US17106946

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Daniel S. Froelich

IPC: G06F11/22 ,  G06F13/42

Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

公开(公告)号：US20180267850A1

公开(公告)日：2018-09-20

申请号：US15761405

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

IPC: G06F11/08 ,  G06F11/22 ,  G06F13/14 ,  H04L1/00

CPC classification number: G06F11/08 ,  G06F11/1004 ,  G06F11/221 ,  G06F13/14 ,  H04L1/0061

Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

公开(公告)号：US20160377679A1

公开(公告)日：2016-12-29

申请号：US15039515

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Daniel S. Froelich ,  Debendra Das Sharma

IPC: G01R31/317 ,  G01R31/3177

Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Abstract translation: 生成测试模式信号以包括测试模式和错误报告序列。 测试模式信号在包括一个或多个扩展设备和两个或更多个子链接的链路上发送。 测试模式信号将被发送在特定的一个子链路上，并且由接收设备使用以识别特定子链路上的错误。 错误报告序列将用错误信息进行编码，以描述多个子链接中的子链接的错误状态。