公开(公告)号：US10386722B2

公开(公告)日：2019-08-20

申请号：US15122620

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Yan A. Borodovsky ,  Donald W. Nelson ,  Mark C. Phillips

IPC: G06F7/20 ,  G03F9/00 ,  H01J3/14 ,  H01J37/04 ,  H01J37/20 ,  H01J37/30 ,  H01J37/302 ,  H01J37/317 ,  H01L21/027 ,  H01L21/311 ,  G03F7/20 ,  G21K5/10

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. A scan direction of the BAA is along a second direction, orthogonal to the first direction.

公开(公告)号：US10332893B2

公开(公告)日：2019-06-25

申请号：US15747414

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  Eric A. Karl

IPC: G11C11/00 ,  H01L27/11 ,  G11C11/418 ,  G11C11/419 ,  G11C11/413

Abstract: Techniques and mechanisms for exchanging signals with one or more transistors at a front side of a semiconductor substrate. In an embodiment, an integrated circuit include a cell—such as a static random access memory (SRAM) cell—comprising transistor structures variously disposed in or on a first side of a substrate. After fabrication of such transistor structures, substrate material may be thinned to expose a second side of the substrate, opposite the first side. A first interconnect and a second interconnect are coupled each to exchange a signal or a voltage. In another embodiment, respective portions of the first interconnect and the second interconnect extend on opposite sides of the substrate, wherein the first side and the second side each extend between such interconnect portions. Positioning of interconnect structures on opposite sides of the substrate allow for performance improvements due to low interconnect resistances.

公开(公告)号：US10297592B2

公开(公告)日：2019-05-21

申请号：US15625714

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L23/538 ,  H01L21/768 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L21/822 ,  H01L29/78

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US20170287905A1

公开(公告)日：2017-10-05

申请号：US15625714

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78 ,  H01L23/538 ,  H01L27/088 ,  H01L27/11 ,  H01L27/12 ,  H01L21/768 ,  H01L21/84

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US20170102615A1

公开(公告)日：2017-04-13

申请号：US15122622

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Yan A. Borodovsky ,  Donald W. Nelson ,  Mark C. Phillips

IPC: G03F7/20 ,  H01J37/317 ,  H01L21/311

CPC classification number: G03F7/2037 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.