公开(公告)号：US11271010B2

公开(公告)日：2022-03-08

申请号：US16629802

申请日：2017-09-20

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Quan Shi ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sourav Chakravarty ,  Barbara A. Chappell ,  M. Clair Webb

IPC: H01L27/118 ,  G06F30/392 ,  H01L27/02 ,  H01L27/092

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US09685436B2

公开(公告)日：2017-06-20

申请号：US14778512

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L27/088 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/768 ,  H01L21/822 ,  H01L23/538 ,  H01L29/78

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US12067338B2

公开(公告)日：2024-08-20

申请号：US17585101

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Quan Shi ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sourav Chakravarty ,  Barbara A. Chappell ,  M. Clair Webb

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/337 ,  G06F30/347 ,  G06F30/373 ,  G06F30/3947 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L27/00 ,  H01L27/11

CPC classification number: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  G06F30/20 ,  G06F30/373 ,  G06F30/3947 ,  H01L2027/11875

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US10700039B2

公开(公告)日：2020-06-30

申请号：US15122382

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  M. Clair Webb ,  Patrick Morrow ,  Kimin Jun

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00 ,  H01L23/427

Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

公开(公告)号：US09490201B2

公开(公告)日：2016-11-08

申请号：US13798575

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  Il-Seok Son

IPC: H01L23/522 ,  H01L21/20 ,  H01L23/00 ,  H01L23/535 ,  H01L21/74 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

Abstract translation: 描述了在器件结构下形成微电子互连的方法。 这些方法和结构可以包括在第一衬底中形成器件层，在第二衬底中形成至少一个布线层，然后将第一衬底与第二衬底耦合，其中第一衬底与第二衬底结合。

公开(公告)号：US10297592B2

公开(公告)日：2019-05-21

申请号：US15625714

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L23/538 ,  H01L21/768 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L21/822 ,  H01L29/78

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US20170287905A1

公开(公告)日：2017-10-05

申请号：US15625714

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78 ,  H01L23/538 ,  H01L27/088 ,  H01L27/11 ,  H01L27/12 ,  H01L21/768 ,  H01L21/84

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US09721898B2

公开(公告)日：2017-08-01

申请号：US15285454

申请日：2016-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  Il-Seok Son

IPC: H01L23/535 ,  H01L21/20 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/74 ,  H01L23/50 ,  H01L27/12

CPC classification number: H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

公开(公告)号：US20170025355A1

公开(公告)日：2017-01-26

申请号：US15285454

申请日：2016-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  II-Seok Son

IPC: H01L23/535 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74

CPC classification number: H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

Abstract translation: 描述了在器件结构下形成微电子互连的方法。 这些方法和结构可以包括在第一衬底中形成器件层，在第二衬底中形成至少一个布线层，然后将第一衬底与第二衬底耦合，其中第一衬底与第二衬底结合。