公开(公告)号：US11456281B2

公开(公告)日：2022-09-27

申请号：US16147742

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Yí Li ,  Zhiguo Qian ,  Prasad Ramanathan ,  Saikumar Jayaraman ,  Kemal Aygun ,  Hector Amador ,  Andrew Collins ,  Jianyong Xie ,  Shigeki Tomishima

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/00

Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

公开(公告)号：US20200006236A1

公开(公告)日：2020-01-02

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393142A1

公开(公告)日：2019-12-26

申请号：US16015739

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L23/498 ,  H01L25/16 ,  H01L49/02 ,  H01L23/42 ,  H01L21/48

Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.

公开(公告)号：US12057413B2

公开(公告)日：2024-08-06

申请号：US16393047

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Arghya Sain ,  Xiaohong Jiang ,  Sujit Sharan ,  Kemal Aygun

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/30111

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US20240006286A1

公开(公告)日：2024-01-04

申请号：US17856795

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Arghya Sain ,  Sujit Sharan ,  Hoai V. Le ,  Jianyong Xie

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/15 ,  H01L24/16 ,  H01L2224/16235

Abstract: A substrate comprising a core structure between a first metallization stack and a second metallization stack. A hardware interface is at a side of the second metallization stack. A first interconnect comprises both a first via portion, and a first trace portion which extends from the first via portion in a first routing layer of the first metallization stack. The first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A second interconnect comprises both a second via portion, and a second trace portion which extends from the second via portion in the first routing layer. The second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A first multi-layer insulator structure adjoins respective sides of the first and second trace portions.

公开(公告)号：US11837549B2

公开(公告)日：2023-12-05

申请号：US18089542

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11817391B2

公开(公告)日：2023-11-14

申请号：US18128960

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11694952B2

公开(公告)日：2023-07-04

申请号：US17665315

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Sujit Sharan ,  Kemal Aygun ,  Zhiguo Qian ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Jianyong Xie

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US11621227B2

公开(公告)日：2023-04-04

申请号：US17540141

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/52 ,  H01L21/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11545416B2

公开(公告)日：2023-01-03

申请号：US16643816

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Jianyong Xie ,  Yidnekachew S. Mekonnen ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.