公开(公告)号：US12224261B2

公开(公告)日：2025-02-11

申请号：US17488174

申请日：2021-09-28

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

公开(公告)号：US11735551B2

公开(公告)日：2023-08-22

申请号：US16363996

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Shawna Liff ,  Xin Yan ,  Numair Ahmed

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/1319 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/171 ,  H01L2224/812 ,  H01L2224/81139 ,  H01L2224/81815 ,  H01L2924/014

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.

公开(公告)号：US20230084375A1

公开(公告)日：2023-03-16

申请号：US17475123

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Priyanka Dobriyal ,  Ankur Agrawal ,  Anna M. Prakash ,  Ann J. Xu ,  Jimin Yao ,  Raiyomand F. Aspandiar ,  Lesley A. Polka Wood ,  Abigail G. Agwai ,  Kayleen L. E. Helms

IPC: H01S5/0237 ,  H01S5/0234

Abstract: An apparatus comprising an integrated circuit chip comprising a first surface region and a second surface region adjacent to the first surface region; a substrate coupled to the integrated circuit chip through a plurality of connections comprising solder; and underfill between the substrate and the integrated circuit chip, wherein the underfill contacts the second surface region, but does not contact the first surface region.

公开(公告)号：US11581238B2

公开(公告)日：2023-02-14

申请号：US17318887

申请日：2021-05-12

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

IPC: H01L23/373 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

公开(公告)号：US11355849B2

公开(公告)日：2022-06-07

申请号：US16635148

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Shawna M. Liff ,  William J. Lambert ,  Zhichao Zhang ,  Robert L. Sankman ,  Sri Chaitra J. Chavali

IPC: H01Q9/04 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/66

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US11049791B1

公开(公告)日：2021-06-29

申请号：US16727703

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

IPC: H01L23/373 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

公开(公告)号：US10256205B2

公开(公告)日：2019-04-09

申请号：US15812754

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

公开(公告)号：US20190096838A1

公开(公告)日：2019-03-28

申请号：US16198429

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

公开(公告)号：US20170287735A1

公开(公告)日：2017-10-05

申请号：US15089136

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Eric Li ,  Shawna Liff

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L21/565 ,  H01L23/3185 ,  H01L2021/60022 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/73204 ,  H01L2224/92125

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.

公开(公告)号：US20170166407A1

公开(公告)日：2017-06-15

申请号：US14969707

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Pramod Malatkar ,  Joshua D. Heppner ,  Jimin Yao

IPC: B65G47/91 ,  H05K13/04 ,  B25J15/06

CPC classification number: B65G47/91 ,  B25J15/0061 ,  B25J15/0616 ,  B65G47/918 ,  H05K13/0409 ,  H05K13/041

Abstract: A pick and place machine includes a frame to adjustably mount, in three dimensions, a plurality of vacuum nozzles over a component to be picked according to a first embodiment a multi-head PnP mechanism may be simple and flexible to train for a wide variety of component and package shapes and sizes. Multiple PnP nozzles are staggered independently in three axes. According to a second embodiment, a PnP mechanism uses an array of self-learning nozzles that adapt by adjusting the z height of individual nozzles to the shape of the object to be picked.