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    Atomic cross-media writes on a storage device
    21.
    发明授权
    Atomic cross-media writes on a storage device 有权

    公开(公告)号：US10915267B2

    公开(公告)日：2021-02-09

    申请号：US15833955

    申请日：2017-12-06

    Applicant: Intel Corporation

    Inventor： Sanjeev N. Trika ,  Peng Li ,  Jawad B. Khan ,  Myron Loewen

    IPC: G06F3/06 ,  H04L29/08 ,  G06F11/07

    Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.

    Techniques For Generating a PAM Eye Diagram in a Receiver
    22.
    发明申请
    Techniques For Generating a PAM Eye Diagram in a Receiver 有权

    公开(公告)号：US20210006439A1

    公开(公告)日：2021-01-07

    申请号：US17029445

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Masashi Shimanouchi ,  Hsinho Wu

    IPC: H04L25/03 ,  H03M1/12 ,  H04L27/01 ,  H04B10/54 ,  H04B10/69

    Abstract: A method facilitates determining transmission loss in a transmission signal and adjusting a receiver setting of a receiver to compensate for the transmission loss. The method includes transmitting a transmission signal from a transmitter and receiving the transmission signal by a first receiver and a second receiver. The method includes digitizing the transmission signal by the first receiver at a first sampling frequency and digitizing the transmission signal by the second receiver at a second sampling frequency that is less than or equal to the first sampling frequency. The method includes generating a PAM-n eye diagram of the transmission signal by the second receiver using digitized signals digitized by the first and second receivers and adjusting an equalizer setting of a first equalizer of the first receiver using eye-opening information of the PAM-n eye diagram where the eye-opening information includes information for the transmission loss.

    Short Link Efficient Interconnect Circuitry
    25.
    发明申请
    Short Link Efficient Interconnect Circuitry 审中-公开

    公开(公告)号：US20190132160A1

    公开(公告)日：2019-05-02

    申请号：US16230974

    申请日：2018-12-21

    Applicant: Intel Corporation

    Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

    IPC: H04L25/03

    Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

    Key-value deduplication
    27.
    发明授权
    Key-value deduplication 有权

    公开(公告)号：US10216445B2

    公开(公告)日：2019-02-26

    申请号：US15639450

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika ,  Vinodh Gopal

    IPC: G06F3/06

    Abstract: One embodiment provides an apparatus. The apparatus include a device storage logic. The device storage logic is to determine a key-based pointer based, at least in part, on a key included in an input key-value (KV) pair received from a host device and to determine whether a unique input KV data block included in the input KV pair is duplicated in a nonvolatile memory circuitry of a storage device. The device storage logic is further to set a descriptor pointer associated with the unique input KV data block to point to a physical nonvolatile memory (NVM) address associated with an existing unique data block and increment a first reference count associated with the existing unique data block, if the unique input KV data block is a duplicate of the existing unique data block, or store the input KV data block to a physical NVM location associated with a selected physical NVM address, set the descriptor pointer to point to the selected physical NVM address and set a second reference count associated with the selected physical NVM address to one, if the unique input KV data block is not duplicated in the NVM circuitry.

    Apparatus, system and method for offloading collision check operations in a storage device
    28.
    发明授权
    Apparatus, system and method for offloading collision check operations in a storage device 有权

    公开(公告)号：US10146440B2

    公开(公告)日：2018-12-04

    申请号：US15385791

    申请日：2016-12-20

    Applicant: INTEL CORPORATION

    Inventor： Peng Li ,  Anand S. Ramalingam ,  Jawad B. Khan ,  William K. Lui ,  Divya Narayanan ,  Sanjeev N. Trika

    IPC: G06F3/06

    Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

    Short link efficient interconnect circuitry
    30.
    发明授权
    Short link efficient interconnect circuitry 有权

    公开(公告)号：US11356303B2

    公开(公告)日：2022-06-07

    申请号：US17214171

    申请日：2021-03-26

    Applicant: Intel Corporation

    Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

    IPC: H04J14/02 ,  H04L25/03 ,  H04L25/14 ,  G06N20/00 ,  H03H21/00

    Abstract: Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

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