公开(公告)号：US20190196907A1

公开(公告)日：2019-06-27

申请号：US16293540

申请日：2019-03-05

Applicant: Intel Corporation

Inventor： Jawad B. KHAN ,  Sanjeev N. TRIKA

IPC: G06F11/10 ,  H03M13/15 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0683 ,  H03M13/154

Abstract: In one example, uncompressed data is compressed and divided into chunks. Each chunk of the compressed data stream is combined with state information to enable each chunk to be independently decompressed. Each of the compressed chunks is then stored on a different storage device along with its associated state information. A compute operation can then be offloaded to the device or node where each chunk is stored. Each chunk can be independently decompressed for execution of the offloaded operation without transferring all chunks to a central location for decompression and performance of the operation.

公开(公告)号：US20190114108A1

公开(公告)日：2019-04-18

申请号：US16211059

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Jawad B. KHAN

IPC: G06F3/06

Abstract: Techniques for offloading operations to access data that is compressed and distributed are disclosed. In one example, a system includes a compute node and a storage node. For example, one or more racks in a data center can include compute and storage nodes. The compute node including one or more processors. The storage node includes one or more storage devices to store a portion of compressed data. Other portions of the compressed data are stored on other nodes. The compute node sends a request to the storage node storing the first chunk of compressed data. The storage node receives the request, decompresses at least part of the portion of the compressed data, and performs the operation on the decompressed part. The storage node can then provide a result from the operation to the compute node. Any part of the compressed data that could not be decompressed by the storage node can be sent to the next storage node. The process continues until all the storage nodes storing the compressed data receive the request, decompress the locally stored data, and perform the operation on the decompressed data.

公开(公告)号：US20190107976A1

公开(公告)日：2019-04-11

申请号：US16213274

申请日：2018-12-07

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes velocity assignment logic to assign a velocity to data that is to be written to a non volatile storage medium. The velocity assignment logic is to accept input information pertaining to an identity of an application that is writing the data, the data type of the data and the state of the application in order to determine the velocity.

公开(公告)号：US20190044536A1

公开(公告)日：2019-02-07

申请号：US16022631

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Omesh Tickoo ,  Wei WU

IPC: H03M13/05 ,  G06F11/10 ,  H03M13/00

CPC classification number: H03M13/05 ,  G06F11/1044 ,  G06F11/1048 ,  H03M13/611

Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.

公开(公告)号：US20190042594A1

公开(公告)日：2019-02-07

申请号：US16001398

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Jawad B. KHAN ,  Piotr WYSOCKI

IPC: G06F17/30 ,  H04L29/08

CPC classification number: G06F16/1834 ,  H04L67/104 ,  H04L67/34 ,  H04L67/42

Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.

公开(公告)号：US20190042460A1

公开(公告)日：2019-02-07

申请号：US15891073

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Rowel S. GARCIA

IPC: G06F12/1009

Abstract: A computer system that includes a host based byte addressable persistent buffer to store a Logical to Physical (L2P) indirection table for a solid-state drive is provided. Shutdown and startup of the computer system is accelerated by storing the L2P indirection table in the host based byte addressable persistent buffer.

公开(公告)号：US20180089088A1

公开(公告)日：2018-03-29

申请号：US15278022

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Andrzej JAKOWSKI ,  Kapil KARKRA ,  Igor KONOPKO ,  Sanjeev N. TRIKA ,  Knut S. GRIMSRUD

IPC: G06F12/0864 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F11/1469 ,  G06F12/0607 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F2201/84 ,  G06F2212/1032 ,  G06F2212/222 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: Provided are an apparatus and method for persisting blocks of data and metadata in a non-volatile memory (NVM) cache. A non-volatile memory (NVM) cache caches blocks of data from the storage of the first block size and metadata for each of the cached blocks of data indicating a status of the cached block of data, including whether the block of data is modified or unmodified, and a location in the storage where the block of data is stored. The non-volatile memory has blocks of a second block size greater than the first block size, wherein one of the blocks in the non-volatile memory stores the block of data from the storage and the metadata for the block of data. A cache manager writes the block of data and the metadata for the block of data to one of the blocks in the non-volatile memory cache and writes the block of data in one of the blocks in the non-volatile memory cache to the storage.

公开(公告)号：US20170336981A1

公开(公告)日：2017-11-23

申请号：US15158536

申请日：2016-05-18

Applicant: INTEL CORPORATION

Inventor： Rowel S. GARCIA ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0608 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/04 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7201

Abstract: Provided are a computer program product, system, and method for dynamically increasing capacity of a storage device. For address mappings, each addressing mapping indicates a storage device block address for a host block address and a compressed block size indicating a number of blocks storing compressed data for data written to the host block address starting at the storage device block address. Write data for a write request to a host block address is compressed to produce compressed data. A block size of the compressed data is less than request block size of the write data for the write request. Indication is made in the address mapping for the host block address of a storage device address at which to start storing the compressed data in the storage device and the compressed block size. The compressed data is sent to the storage device to write at the storage device block address.

公开(公告)号：US20240378150A1

公开(公告)日：2024-11-14

申请号：US18781854

申请日：2024-07-23

Applicant: Intel Corporation

Inventor： Frank T. HADY ,  Sanjeev N. TRIKA

IPC: G06F12/0815 ,  G06F8/41 ,  G06F12/0804

Abstract: An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.

公开(公告)号：US20200264800A1

公开(公告)日：2020-08-20

申请号：US16865566

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Piotr WYSOCKI ,  Sanjeev N. TRIKA ,  Gregory B. TUCKER ,  Jackson ELLIS ,  Jonathan M. HUGHES

IPC: G06F3/06 ,  G06F9/30

Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive. The controller is further to issue commands to one or more EC storage drives to read the old data, compute result data as the old data XOR a galois field coefficient of the one or more EC storage drives multiplied by the intermediate data, and atomically write the old data to the intermediate buffer of the one or more EC storage drives and write the result data to the one or more EC storage drive's NVM. Other embodiments are disclosed and claimed.