公开(公告)号：US20230098467A1

公开(公告)日：2023-03-30

申请号：US17485176

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Patrick THEOFANIS ,  Charles MOKHTARZADEH ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/66

Abstract: Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.

公开(公告)号：US20230096347A1

公开(公告)日：2023-03-30

申请号：US17485202

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Tristan A. TRONIC ,  Anandi ROY ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Sudarat LEE ,  Chelsey DOROW ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a sheet that is a semiconductor. In an embodiment a length dimension of the sheet and a width dimension of the sheet are greater than a thickness dimension of the sheet. In an embodiment, a gate structure is around the sheet, and a first spacer is adjacent to a first end of the gate structure, and a second spacer adjacent to a second end of the gate structure. In an embodiment, a source contact is around the sheet and adjacent to the first spacer, and a drain contact is around the sheet and adjacent to the second spacer.

公开(公告)号：US20230088101A1

公开(公告)日：2023-03-23

申请号：US17482232

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Thin film transistors having edge-modulated two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a device layer including a two-dimensional (2D) material layer above a substrate, the 2D material layer including a center portion and first and second edge portions, the center portion consisting essentially of molybdenum or tungsten and of sulfur or selenium, and the first and second edge portions including molybdenum or tungsten and including tellurium.

公开(公告)号：US20210305358A1

公开(公告)日：2021-09-30

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20160190060A1

公开(公告)日：2016-06-30

申请号：US14909736

申请日：2013-09-27

Applicant: Rami HOURANI ,  INTEL CORPORATION

Inventor： Robert L. Bristol ,  James M. BLACKWELL ,  Scott B. CLENDENNING ,  Florian GSTREIN ,  Eungnak HAN ,  Grant M. KLOSTER ,  Jeanette M. ROBERTS ,  Patricio E. ROMERO ,  Rami HOURANI

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：US20240088143A1

公开(公告)日：2024-03-14

申请号：US18516595

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Scott B. CLENDENNING ,  Jessica TORRES ,  Lukas BAUMGARTEL ,  Kiran CHIKKADI ,  Diane LANCASTER ,  Matthew V. METZ ,  Florian GSTREIN ,  Martin M. MITAN ,  Rami HOURANI

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/538 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5384 ,  H01L23/5389 ,  H01L27/0924 ,  H01L21/823462 ,  H01L21/823871

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20230113614A1

公开(公告)日：2023-04-13

申请号：US17485185

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Chelsey DOROW ,  Carl NAYLOR ,  Kirby MAXEY ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Urusa ALAAN ,  Tristan A. TRONIC

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/12

Abstract: Thin film transistors having CMOS functionality integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first device including a first two-dimensional (2D) material layer, and a first gate stack around the first 2D material layer. The first gate stack has a gate electrode around a gate dielectric layer. A second device is stacked on the first device. The second device includes a second 2D material layer, and a second gate stack around the second 2D material layer. The second gate stack has a gate electrode around a gate dielectric layer. The second 2D material layer has a composition different than a composition of the first 2D material layer.

公开(公告)号：US20230102695A1

公开(公告)日：2023-03-30

申请号：US17485301

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L29/45 ,  H01L29/417 ,  H01L27/088

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, to IC structures with graphene contacts. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230101760A1

公开(公告)日：2023-03-30

申请号：US17485225

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Chelsey DOROW ,  Sudarat LEE ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Tristan A. TRONIC ,  Shriram SHIVARAMAN ,  Ashish Verma PENUMATCHA

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L23/48 ,  H01L29/786

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

公开(公告)号：US20230101370A1

公开(公告)日：2023-03-30

申请号：US17485181

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sudarat LEE ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Charles MOKHTARZADEH ,  Ashish Verma PENUMATCHA ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Thin film transistors having multi-layer gate dielectric structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is over the 2D material layer, the gate stack having a first side opposite a second side, and the gate stack having a gate electrode around a gate dielectric structure. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer are continuous with a layer of the gate dielectric structure. A first conductive structure is coupled to the 2D material layer and adjacent to the first gate spacer. A second conductive structure is coupled to the 2D material layer and adjacent to the second gate spacer.