公开(公告)号：US20200035659A1

公开(公告)日：2020-01-30

申请号：US16590057

申请日：2019-10-01

Applicant: Intel Corporation

Inventor： Stefan Rusu

IPC: H01L25/18 ,  G06F15/76 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L25/00

Abstract: A method is described for stacking a plurality of cores. For example, one embodiment comprises: mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die; and vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die.

公开(公告)号：US10236209B2

公开(公告)日：2019-03-19

申请号：US14583015

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sujit Sharan ,  Ravindranath Mahajan ,  Stefan Rusu ,  Donald S. Gardner

IPC: H01L21/78 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02 ,  H01L23/538 ,  H01L23/522 ,  H01L27/08

Abstract: Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

公开(公告)号：US10128855B2

公开(公告)日：2018-11-13

申请号：US15214364

申请日：2016-07-19

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Stefan Rusu

IPC: H03L7/00 ,  H03L7/091 ,  H01L23/48 ,  G06F13/40 ,  H04L7/00 ,  H03L7/07 ,  H03L7/081 ,  G06F1/12 ,  H01L25/065

Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

公开(公告)号：US10007749B2

公开(公告)日：2018-06-26

申请号：US14494190

申请日：2014-09-23

Applicant: Intel Corporation

Inventor： Roger K. Cheng ,  Stefan Rusu ,  Aaron Martin

IPC: G06F17/50 ,  H03M1/12 ,  H03M1/66

CPC classification number: G06F17/5063 ,  G06F2217/78 ,  H03M1/12 ,  H03M1/66

Abstract: Described is an apparatus which comprises: logic to convert output of at least one sensor to a digital sensing signal; a router coupled to the sensor, the router to receive the digital sensing signal and to map into circuit data; and one or more communication interfaces, coupled to the router, to forward circuit data to a circuit endpoint. Described is a method which comprises: providing one or more digital sensing signals from a plurality of sensors; receiving the one or more digital sensing signals; generating packets of data using the one or more digital sensing signals; and providing the packets of data to one or more destinations.

公开(公告)号：US09385728B2

公开(公告)日：2016-07-05

申请号：US14513024

申请日：2014-10-13

Applicant: Intel Corporation

Inventor： Choupin Huang ,  Vijaya K. Boddu ,  Stefan Rusu ,  Nicholas B Peterson

IPC: H03L7/07 ,  G06F3/16 ,  H03L7/089 ,  H03L7/08

CPC classification number: H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.

Abstract translation: 集成时钟差分缓冲。 具有第一时钟比率的第一锁相环（PLL）电路被耦合以接收输入差分时钟信号。 第一PLL电路产生第一参考时钟信号。 具有第二时钟比的第二PLL电路被耦合以接收输入差分时钟信号。 第二个PLL电路产生第二个参考时钟信号。 耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应于第一参考时钟信号的第一差分参考时钟信号。 第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供对应于第二参考时钟信号的第二差分参考时钟信号。 第一PLL电路，第二PLL电路，第一组输出缓冲器和第二组输出缓冲器驻留在还具有至少接收第一差分参考时钟信号的管芯的集成电路封装中。