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公开(公告)号:US20230153174A1
公开(公告)日:2023-05-18
申请号:US17528581
申请日:2021-11-17
Applicant: Intel Corporation
Inventor: Akhilesh S. THYAGATURU , Vinodh GOPAL , Saidulu ALDAS , Anthony W. MOORE
IPC: G06F9/50
CPC classification number: G06F9/5083 , G06F9/5044 , G06F9/505
Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes circuitry to provide access to an accelerator device on a second platform to perform a workload in response to communication with a device driver executed by a first platform. In some examples, the first platform and second platform are connected by a network and wherein the accelerator device satisfies a selection criteria and wherein the selection criteria comprises a device type. In some examples, the accelerator device on the second platform is accessible to an application via the device driver.
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公开(公告)号:US20220263770A1
公开(公告)日:2022-08-18
申请号:US17179249
申请日:2021-02-18
Applicant: Intel Corporation
Inventor: Akhilesh S. THYAGATURU , Vinodh GOPAL , Patrick J. HART , Christin FENTER
IPC: H04L12/911 , H04L12/923 , H04L12/721 , H04L12/26 , G06F9/455
Abstract: Methods and apparatus for application-to-application resource reservation schemes for precision networking. Hardware resources, such as interconnects and processing resources, are reserved for forwarding and processing data along flow paths for end-to-end delivery of data between applications running on respective platforms communicating over a network. Operating system and/or hypervisor resources are also reserved. The reservations may be based per application, per virtual machine (VM), or per container, and reservations for multiple applications/VMs/containers are supported. The interconnects include chip-to-chip, socket-to-socket (for multi-socket platforms), and die-to-die interconnects. Reservations for on-chip fabrics are also supported. Under one approach, an orchestrator is used to manage resources reservations by sending resources reservation requests to a platform's operating system or hypervisor, with the operating system/hypervisor configuring the platform hardware resources to effect based on the reserved resources. The method and apparatus may be used to implement flow paths having deterministic latencies and/or meet SLA QoS requirements.
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公开(公告)号:US20220103345A1
公开(公告)日:2022-03-31
申请号:US17547018
申请日:2021-12-09
Applicant: Intel Corporation
Inventor: Tomasz KANTECKI , Wei LI , Wajdi FEGHALI , James GUILFORD , Vinodh GOPAL
IPC: H04L9/06
Abstract: Methods, apparatus, and software for hashing data. The methods and apparatus employ novel improvements to hash algorithms, such as a SHA-2 hash algorithm to reduce computations and increase performance. In one aspect, calculation of SHA-2 message scheduling and SHA compression operations are separated under which an SHA-2 message schedule is applied to multiple rounds of SHA compression operations over multiple chunks of data for the data item being hashed. In another aspect, the SHA-2 message schedule is implemented such that message schedules for multiple message words or data blocks are performed in parallel. The approaches may be employed to reduce hash calculations for various purposes, including generating Filecoin nodes.
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公开(公告)号:US20210314359A1
公开(公告)日:2021-10-07
申请号:US17349247
申请日:2021-06-16
Applicant: Intel Corporation
Inventor: Akhilesh S. THYAGATURU , Vinodh GOPAL
IPC: H04L29/06
Abstract: Methods, apparatus, and software for efficient encryption in virtual private network (VPN) sessions. A VPN link and an auxiliary link (and associated sessions) are established between computing platforms to support end-to-end communication between respective application running on the platforms. The VPN link may employ a conventional VPN protocol such as TLS or IPsec, while the auxiliary link comprises a NULL encryption VPN tunnel. To transfer data, a determination is made to whether the data are encrypted or non-encrypted. Encrypted data are transferred over the auxiliary link to avoid re-encryption of the data. Non-encrypted are transferred over the VPN link. TLS and IPsec VPN agents may be used to assist in setting up the VPN and auxiliary sessions. The techniques avoid double encryption of VPN traffic, while ensuring that various types of traffic transferred between platforms is encrypted.
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25.
公开(公告)号:US20200007329A1
公开(公告)日:2020-01-02
申请号:US16022619
申请日:2018-06-28
Applicant: Intel Corporation
Inventor: James GUILFORD , Vinodh GOPAL , Kirk YAP
Abstract: Disclosed embodiments relate to encrypting or decrypting confidential data with additional authentication data by an accelerator and a processor. In one example, a processor includes processor circuitry to compute a first hash of a first block of data stored in a memory, store the first hash in the memory, and generate an authentication tag based in part on a second hash. The processor further includes accelerator circuitry to obtain the first hash from the memory, decrypt a second block of data using the first hash, and compute the second hash based in part on the first hash and the second block of data.
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公开(公告)号:US20190332378A1
公开(公告)日:2019-10-31
申请号:US16450319
申请日:2019-06-24
Applicant: Intel Corporation
Inventor: Kirk S. YAP , Gilbert M. WOLRICH , James D. GUILFORD , Vinodh GOPAL , Erdinc OZTURK , Sean M. GULLEY , Wajdi K. FEGHALI , Martin G. DIXON
IPC: G06F9/30 , G06F9/38 , G06F12/1027 , G06F12/0875 , H04L9/06 , G06F15/80 , H04L9/32 , G09C1/00 , G06F13/42 , G06F13/40 , G06F13/28 , G06F21/60 , G06F12/0897
Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
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公开(公告)号:US20190116025A1
公开(公告)日:2019-04-18
申请号:US16017519
申请日:2018-06-25
Applicant: Intel Corporation
Inventor: Gilbert M. WOLRICH , Kirk S. YAP , Vinodh GOPAL , James D. GUILFORD
CPC classification number: H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
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28.
公开(公告)号:US20190034493A1
公开(公告)日:2019-01-31
申请号:US15856245
申请日:2017-12-28
Applicant: Intel Corporation
Inventor: Vinodh GOPAL , Kirk S. YAP , James GUILFORD , Simon N. PEFFERS
IPC: G06F17/30
Abstract: Data element filter logic (“hardware accelerator”) in a processor that offloads computation for an in-memory database select/extract operation from a Central Processing Unit (CPU) core in the processor is provided. The Data element filter logic provides a balanced performance across an entire range of widths (number of bits) of data elements in a column-oriented Database Management System.
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公开(公告)号:US20180095720A1
公开(公告)日:2018-04-05
申请号:US15282544
申请日:2016-09-30
Applicant: Intel Corporation
Inventor: Vinodh GOPAL , Jawad B. KHAN , Sanjeev N. TRIKA
CPC classification number: G06F7/20 , G06F16/2255 , G06F16/24553
Abstract: A storage device is described. The storage device includes non volatile memory having data storage resources organized into slots to store chunks of data. The storage device includes memory to store a data pointer table having groups of pointers to the slots. Each of the groups correspond to a respective block that is stored in the non volatile memory. Certain ones of the pointers are to have an associated set of hashes of different segments of the respective chunks that are pointed to by the certain ones of the pointers. The storage device includes a search module to implement a search function within the storage device that hashes a search key and compares the hashed search key to the hashes of the different segments to identify a possible match to the search key.
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公开(公告)号:US20170147348A1
公开(公告)日:2017-05-25
申请号:US15396563
申请日:2016-12-31
Applicant: Intel Corporation
Inventor: Kirk S. YAP , Gilbert M. WOLRICH , James D. GUILFORD , Vinodh GOPAL , Erdinc OZTURK , Sean M. GULLEY , Wajdi K. FEGHALI , Martin G. DIXON
IPC: G06F9/30 , H04L9/06 , G06F12/0875 , G06F12/1027 , G06F15/80 , G06F9/38
CPC classification number: G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30156 , G06F9/3802 , G06F9/384 , G06F9/3855 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F13/28 , G06F13/4068 , G06F13/4282 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , G06F2213/0026 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/122
Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
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