公开(公告)号：US12243148B2

公开(公告)日：2025-03-04

申请号：US17070095

申请日：2020-10-14

Applicant: Intel Corporation

Inventor： Vivek De ,  Ram Krishnamurthy ,  Amit Agarwal ,  Steven Hsu ,  Monodeep Kar

IPC: G06T15/00 ,  G06T15/06

Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.

公开(公告)号：US11669114B2

公开(公告)日：2023-06-06

申请号：US17528241

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Sriram R. Vangal ,  Jayanth Mallanayakanahalli Devaraju ,  Vivek De ,  Robert Milstrey ,  Stephen H. Gunther

IPC: G05F1/46 ,  G06F16/901 ,  G06F1/3203 ,  G06F1/28 ,  G06F16/90 ,  G06F1/32

CPC classification number: G05F1/462 ,  G06F1/28 ,  G06F1/3203 ,  G06F16/9017

Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.

公开(公告)号：US11281281B2

公开(公告)日：2022-03-22

申请号：US16956447

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Jayanth M. Devaraju ,  Vivek De ,  Sriram Vangal

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: Circuitry is provided to control a performance level of a processing device depending on two or more operating points of the processing device. An operating point has a corresponding frequency and a corresponding voltage. The performance-level control circuitry arranged to cross-multiply parameters corresponding to a first operating point and a second, different operating point of the processing device. A relative energy expenditure of the first operating point and the second operating point is determined based on the cross multiplication. An operating point of the processing device is selected depending on the determined relative energy expenditure. An apparatus having the performance level control circuitry, machine readable instructions for implementing the performance level control and a corresponding method are also provided.

公开(公告)号：US20210203228A1

公开(公告)日：2021-07-01

申请号：US16727759

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Vivek De

IPC: H02M3/158 ,  H03L5/00 ,  H02M1/088 ,  H02N13/00

Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

公开(公告)号：US10739804B2

公开(公告)日：2020-08-11

申请号：US15712813

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Sriram R. Vangal ,  Turbo Majumder ,  Vivek De

IPC: G05F1/66 ,  G05F1/46 ,  G06F1/3296 ,  H02M3/158 ,  H02M1/08 ,  H02M3/157

Abstract: Various embodiments of the invention may be used to find a combination of voltage and frequency that results in a minimum amount of energy consumption in a digital system, including energy consumed by the system's voltage regulator (VR). The process may involve finding a separate point of minimum energy consumption for each of several different modes of the VR, where a mode is the ratio of Vin to Vout for that VR. The smallest value of those points may then be selected as the overall minimum. The process for making this determination may be performed in situ while the device is in operation, and may encompass changes in operational temperature, load, and process variations.

公开(公告)号：US10530254B2

公开(公告)日：2020-01-07

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

公开(公告)号：US10528473B2

公开(公告)日：2020-01-07

申请号：US15621401

申请日：2017-06-13

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0804 ,  G06F1/3234

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.