公开(公告)号：US11495672B2

公开(公告)日：2022-11-08

申请号：US16023024

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Dax M. Crum ,  Biswajeet Guha ,  William Hsu ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.

公开(公告)号：US11335807B2

公开(公告)日：2022-05-17

申请号：US16024046

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Stephen M. Cea ,  Biswajeet Guha ,  Tahir Ghani ,  William Hsu

IPC: H01L29/78 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

公开(公告)号：US11302790B2

公开(公告)日：2022-04-12

申请号：US16772631

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Biswajeet Guha ,  Mark Armstrong ,  William Hsu ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/16 ,  H01L29/20

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20190393350A1

公开(公告)日：2019-12-26

申请号：US16013329

申请日：2018-06-20

Applicant: INTEL CORPORATION

Inventor： Erica J. Thompson ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US12302632B2

公开(公告)日：2025-05-13

申请号：US18523637

申请日：2023-11-29

Applicant: Intel Corporation

Inventor： Jun Sung Kang ,  Kai Loon Cheong ,  Erica J. Thompson ,  Biswajeet Guha ,  William Hsu ,  Dax M. Crum ,  Tahir Ghani ,  Bruce Beattie

IPC: H10D84/85 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10 ,  H10D62/832 ,  H10D64/01 ,  H10D64/27 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

公开(公告)号：US12272737B2

公开(公告)日：2025-04-08

申请号：US18368428

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US12166031B2

公开(公告)日：2024-12-10

申请号：US17131616

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Brian Greene ,  Daniel Schulman ,  William Hsu ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/87

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

公开(公告)号：US12068314B2

公开(公告)日：2024-08-20

申请号：US17026047

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  William Hsu ,  Biswajeet Guha ,  Martin Weiss ,  Apratim Dhar ,  William T. Blanton ,  John H. Irby, IV ,  James F. Bondi ,  Michael K. Harper ,  Charles H. Wallace ,  Tahir Ghani ,  Benedict A. Samuel ,  Stefan Dickert

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US11929396B2

公开(公告)日：2024-03-12

申请号：US17725471

申请日：2022-04-20

Applicant: INTEL CORPORATION

Inventor： William Hsu ,  Biswajeet Guha ,  Leonard Guler ,  Souvik Chakrabarty ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  B82Y10/00

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

公开(公告)号：US11894368B2

公开(公告)日：2024-02-06

申请号：US16727355

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/775 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.