公开(公告)号：US20240176584A1

公开(公告)日：2024-05-30

申请号：US18071230

申请日：2022-11-29

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Andrea Fasoli ,  Ankur Agrawal ,  Kyu-hyoun Kim ,  Chi-Chun LIU ,  Mauricio J. Serrano ,  Monodeep Kar ,  Naigang Wang ,  Leland Chang

IPC: G06F7/523

CPC classification number: G06F7/523

Abstract: An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result.

公开(公告)号：US11227231B2

公开(公告)日：2022-01-18

申请号：US15972108

申请日：2018-05-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lingfei Wu ,  Kun Xu ,  Pin-Yu Chen ,  Chia-Yu Chen

IPC: G06N20/00 ,  G06F16/28

Abstract: A method and system of analyzing a symbolic sequence is provided. Metadata of a symbolic sequence is received from a computing device of an owner. A set of R random sequences are generated based on the received metadata and sent to the computing device of the owner of the symbolic sequence for computation of a feature matrix based on the set of R random sequences and the symbolic sequence. The feature matrix is received from the computing device of the owner. Upon determining that an inner product of the feature matrix is below a threshold accuracy, the iterative process returns to generating R random sequences. Upon determining that the inner product of the feature matrix is at or above the threshold accuracy, the feature matrix is categorized based on machine learning. The categorized global feature matrix is sent to be displayed on a user interface of the computing device of the owner.

公开(公告)号：US20210064372A1

公开(公告)日：2021-03-04

申请号：US16558536

申请日：2019-09-03

Applicant: International Business Machines Corporation

Inventor： Xiao Sun ,  Chia-Yu Chen ,  Naigang Wang ,  Jungwook Choi ,  Kailash Gopalakrishnan

IPC: G06F9/30 ,  G06F7/483 ,  G06N5/04 ,  G06N20/00 ,  G06F17/18

Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor includes first and second sets of arithmetic units having first and second precision for floating-point computations, the second precision being lower than the first precision. The processor is configured to obtain a machine learning model trained in the first precision, to utilize the second set of arithmetic units to perform inference on input data, to utilize the first set of arithmetic units to generate feedback for updating parameters of the second set of arithmetic units based on the inference performed on the input data by the second set of arithmetic units, to tune parameters of the second set of arithmetic units based at least in part on the feedback generated by the first set of arithmetic units, and to utilize the second set of arithmetic units with the tuned parameters to generate inference results.

公开(公告)号：US10777557B2

公开(公告)日：2020-09-15

申请号：US16672994

申请日：2019-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/18 ,  H01L29/165

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

公开(公告)号：US20200175422A1

公开(公告)日：2020-06-04

申请号：US16204770

申请日：2018-11-29

Applicant: International Business Machines Corporation

Inventor： Wei Zhang ,  Chia-Yu Chen

IPC: G06N20/20 ,  G06N7/08

Abstract: Systems, computer-implemented methods, and computer program products to facilitate gradient weight compression are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a pointer component that can identify one or more compressed gradient weights not present in a first concatenated compressed gradient weight. The computer executable components can further comprise a compression component that can compute a second concatenated compressed gradient weight based on the one or more compressed gradient weights to update a weight of a learning entity of a machine learning system.

公开(公告)号：US10658391B2

公开(公告)日：2020-05-19

申请号：US15381441

申请日：2016-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L27/12 ,  H01L21/30 ,  H01L21/82 ,  H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/04 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L21/308

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

公开(公告)号：US10579583B2

公开(公告)日：2020-03-03

申请号：US15232177

申请日：2016-08-09

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Pierce I-Jen Chuang ,  Li-Wen Hung ,  Jui-Hsin Lai

IPC: G06F7/58 ,  G06F15/78 ,  G06N3/063 ,  G06N3/08

Abstract: A random number signal generator used for performing dropout or weight initialization for a node in a neural network. The random number signal generator includes a transistor which generates a random noise signal. The transistor includes a substrate, source and drain regions formed in the substrate, a first insulating layer formed over a channel of the transistor, a first trapping layer formed over the first insulating layer, a second insulating layer formed over the first trapping layer, and a second trapping layer formed over the second insulating layer. One or more traps in the first and second trapping layers are configured to capture or release one or more carriers flowing through the channel region. The random noise signal is generated as a function of one or more carrier being captured or released by the one or more traps.

公开(公告)号：US09923074B2

公开(公告)日：2018-03-20

申请号：US15629938

申请日：2017-06-22

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L21/225 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/08 ,  H01L21/311 ,  H01L29/49 ,  H01L21/3065 ,  H01L21/285 ,  H01L29/40 ,  H01L23/485

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US20170344485A1

公开(公告)日：2017-11-30

申请号：US15164551

申请日：2016-05-25

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Jungwook Choi ,  Shu-Jen Han ,  Yinglong Xia

IPC: G06F12/0875 ,  G06F9/30

Abstract: Techniques that facilitate heterogeneous runahead processing for a processor core are provided. In one example, a first core performs a first execution of a first sequence of instructions, where the first core is communicatively coupled to a first cache memory. A second core performs a second execution of at least a portion of the first sequence of instructions and a first determination that data associated with the first sequence of instructions fails to be stored in the first cache memory, where the first determination is performed concurrent with the first execution, and the first core executes a second sequence of instructions based on a second determination that the second core is performing the second execution of at least a portion of the first sequence of instructions.

公开(公告)号：US20170288035A1

公开(公告)日：2017-10-05

申请号：US15629910

申请日：2017-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/08 ,  H01L21/311 ,  H01L29/49 ,  H01L21/3065 ,  H01L29/45 ,  H01L21/285 ,  H01L29/40 ,  H01L23/485 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.