公开(公告)号：US09881937B2

公开(公告)日：2018-01-30

申请号：US15397170

申请日：2017-01-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/308 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

公开(公告)号：US20160343861A1

公开(公告)日：2016-11-24

申请号：US14719829

申请日：2015-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract translation: 提供一种半导体结构，其包括具有端壁并从衬底向上延伸的半导体鳍部。 栅极结构跨越半导体鳍片部分的一部分。 第一组栅极间隔物位于栅极结构的相对的侧壁表面上; 并且第二组栅极间隔物位于第一组栅极间隔物的侧壁上。 第二组栅极间隔物的一个栅极间隔物具有直接接触半导体鳍片部分的端壁的下部。

公开(公告)号：US09293221B1

公开(公告)日：2016-03-22

申请号：US14632017

申请日：2015-02-26

Applicant: International Business Machines Corporation

Inventor： Derrick Liu ,  Chun-Chen Yeh

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/40 ,  G11C17/16 ,  H01L27/11206

Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.

公开(公告)号：US20200219247A1

公开(公告)日：2020-07-09

申请号：US16822471

申请日：2020-03-18

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Liying Jiang ,  Derrick Liu ,  Jingyun Zhang ,  Huimei Zhou

IPC: G06T7/00 ,  G06N20/00 ,  G06K9/62 ,  G06K9/46

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

公开(公告)号：US10664966B2

公开(公告)日：2020-05-26

申请号：US15879530

申请日：2018-01-25

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Liying Jiang ,  Derrick Liu ,  Jingyun Zhang ,  Huimei Zhou

IPC: G06K9/00 ,  G06K9/62 ,  G06K9/40 ,  G06T7/00 ,  G06N20/00 ,  G06K9/46 ,  G06F16/28

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

公开(公告)号：US20190228519A1

公开(公告)日：2019-07-25

申请号：US15879530

申请日：2018-01-25

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Liying Jiang ,  Derrick Liu ,  Jingyun Zhang ,  Huimei Zhou

IPC: G06T7/00 ,  G06F15/18

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

公开(公告)号：US10147839B2

公开(公告)日：2018-12-04

申请号：US14828663

申请日：2015-08-18

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

IPC: H01L31/18 ,  H01L31/0224 ,  H01L33/00 ,  H01L33/42 ,  H01L51/00 ,  B82Y10/00 ,  B82Y30/00 ,  H01B1/24 ,  H05K3/10

Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in a disorderly arrangement on a substrate. The metal silicide nanowire network can be formed by applying a solution that contains silicon nanowires onto the substrate, forming a metal layer on the silicon nanowires, and performing a silicidation anneal such that the metal silicide nanowires are fused together in a disorderly arrangement, forming a mesh. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

公开(公告)号：US10147725B2

公开(公告)日：2018-12-04

申请号：US14968134

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Gauri Karve ,  Derrick Liu ,  Robert R. Robison ,  Gen Tsutsui ,  Reinaldo A. Vega ,  Koji Watanabe

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/49 ,  H01L29/161 ,  H01L29/16 ,  H01L21/02 ,  H01L29/40

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.

公开(公告)号：US20180083017A1

公开(公告)日：2018-03-22

申请号：US15823022

申请日：2017-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8258 ,  H01L27/02

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US20180083016A1

公开(公告)日：2018-03-22

申请号：US15787768

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8258

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.