公开(公告)号：US09524916B2

公开(公告)日：2016-12-20

申请号：US13664903

申请日：2012-10-31

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Naftali E. Lustig ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/66 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology.

Abstract translation: 一种用于TDDB测量的结构，一种以减小的间隔确定TDDB的方法。 该结构包括在下电介质层的顶表面上的上电介质层，上电介质层的底表面和下电介质层的顶表面限定界面; 形成在下介电层中的第一线; 形成在上电介质层中的第二线; 并且其中在平行于界面的方向上测量的第一线和第二线之间的距离低于制造技术的光刻分辨率极限。

公开(公告)号：US09431293B2

公开(公告)日：2016-08-30

申请号：US14721460

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

公开(公告)号：US09360525B2

公开(公告)日：2016-06-07

申请号：US14188728

申请日：2014-02-25

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC: G01R31/327 ,  H01L23/58 ,  G01R31/02 ,  G01R31/04 ,  G01R31/07

CPC classification number: H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Abstract translation: 线路的后端（BEOL）保险丝结构具有一叠通孔。 通孔的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬里和种子层的弱点导致电迁移（EM）故障的较高概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔丝编程之后受损区域的程度，并防止损坏的介质区域的进一步传播。

公开(公告)号：US09190360B2

公开(公告)日：2015-11-17

申请号：US14181960

申请日：2014-02-17

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L21/66 ,  H01L23/544 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/32139 ,  G09C1/00 ,  H01L21/0273 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76885 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/57 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2224/05097 ,  H04L9/3278 ,  H04L2209/12

Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.

Abstract translation: 有机材料层被光刻图案化以包括线和空间的直线阵列部分。 在一个实施例中，有机材料层可以是利用在有机平坦化层的图案化期间消耗的光致抗蚀剂层进行图案化的有机平坦化层。 有机平面化层在暴露于含卤素气体时的体积膨胀导致线性阵列的部分在随机位置崩溃。 在另一个实施方案中，选择光致抗蚀剂层的高度，使得光致抗蚀剂层的线性阵列部分在机械上不稳定并产生随机光刻胶塌陷。 由于有机材料层的崩溃引起的包括随机修饰的图案被转移到下层中，以产生具有短路或开放的随机电气中断的导电材料线的阵列。 具有随机短路的结构可用作物理不可克隆功能。

公开(公告)号：US09123726B2

公开(公告)日：2015-09-01

申请号：US13964772

申请日：2013-08-12

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Abstract translation: 一种形成集成电路器件的布线结构的方法包括在层间电介质（ILD）层内形成第一金属线，并在与第一金属线相邻的ILD层中形成第二金属线; 掩蔽所述第一和第二金属线的选定区域; 以周期性间隔选择性地在第一和第二金属线的暴露区域上电镀金属帽区域，使得单个金属线的相邻金属帽区域之间的间隔对应于临界长度L，在该临界长度L处，背应力梯度平衡电迁移力 在各个金属线上，以抑制电子的质量传递; 并且其中所述第一金属线的金属帽区域沿着共同的纵向轴线相对于所述第二金属线的金属帽区域以交错位置形成。

公开(公告)号：US09059170B2

公开(公告)日：2015-06-16

申请号：US13760488

申请日：2013-02-06

Applicant: International Business Machines Corporation

Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Wai-Kin Li ,  Erdem Kaltalioglu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.

Abstract translation: 一种电子熔丝结构，包括包含Mx金属的Mx电平和Mx电平以上的Mx + 1电平，Mx + 1电平包括Mx + 1金属和将Mx金属电连接到Mx + 1金属的通孔 垂直取向，其中Mx + 1金属包括厚部分和薄部分，并且其中Mx金属，Mx + 1金属和通孔基本上填充有导电材料。

公开(公告)号：US20150056806A1

公开(公告)日：2015-02-26

申请号：US14529431

申请日：2014-10-31

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Ronald G. Filippi ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC: H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Abstract translation: 一种改进的互连结构，其包括具有嵌入其中的导电特征的介电层，所述导电特征具有与介电层的第二顶表面基本共面的第一顶表面; 金属盖层直接位于第一顶表面上，其中金属盖层基本上不延伸到第二顶表面上; 位于所述第二顶表面上的第一电介质盖层，其中所述第一电介质盖层基本上不延伸到所述第一顶表面上，并且所述第一电介质盖层比所述金属盖层厚; 以及金属盖层和第一电介质盖层上的第二电介质盖层。 还提供了形成互连结构的方法。

公开(公告)号：US20150028484A1

公开(公告)日：2015-01-29

申请号：US14465255

申请日：2014-08-21

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.

Abstract translation: 公开了一种用于防止由于电迁移和时间依赖介电击穿而导致的集成电路故障的方法和结构。 在金属互连线（通常为铜（Cu））上选择性地形成随机图案化的金属覆盖层，金属帽段之间的间隙距离小于临界长度（对于短长度效应）。 由于Cu /金属帽接口的扩散率比对于Cu /电介质盖接口的扩散率低，所以具有金属帽的区域用作扩散阻挡层。

公开(公告)号：US20150021736A1

公开(公告)日：2015-01-22

申请号：US14508471

申请日：2014-10-07

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  John A. Fitzsimmons ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76886 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.

Abstract translation: 一种具有Mx级的电子熔丝结构，其包括在Mx电介质的至少一部分上方的Mx电介质，熔丝线，Mx帽电介质，以及直接位于熔丝线的至少一部分上的Mx帽电介质的改质部分 ，其中Mx帽电介质的改性部分在化学上不同于Mx帽电介质的其余部分，Mx + 1电平包括Mx + 1电介质，Mx + 1电极，Mx + 1金属，Mx + 1帽电介质 Mx + 1电介质和第一Mx + 1金属，其中Mx + 1电平高于Mx电平，以及第一通孔将熔丝线电连接到第一Mx + 1金属。

公开(公告)号：US08889491B2

公开(公告)日：2014-11-18

申请号：US13751238

申请日：2013-01-28

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  John A. Fitzsimmons ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/82 ,  H01L23/48

CPC classification number: H01L23/5256 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76886 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.

Abstract translation: 一种具有Mx级的电子熔丝结构，其包括在Mx电介质的至少一部分上方的Mx电介质，熔丝线，Mx帽电介质，以及直接位于熔丝线的至少一部分上的Mx帽电介质的改质部分 ，其中Mx帽电介质的改性部分在化学上不同于Mx帽电介质的其余部分，Mx + 1电平包括Mx + 1电介质，Mx + 1电极，Mx + 1金属，Mx + 1帽电介质 Mx + 1电介质和第一Mx + 1金属，其中Mx + 1电平高于Mx电平，以及第一通孔将熔丝线电连接到第一Mx + 1金属。