公开(公告)号：US20170286108A1

公开(公告)日：2017-10-05

申请号：US15086947

申请日：2016-03-31

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas Winters FOX ,  Arpith C. JACOB ,  Hans Mikael Jacobson ,  Ravi Nair ,  Kevin John Patrick O'Brien ,  Daniel Arthur Prener

IPC: G06F9/30

Abstract: A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.

公开(公告)号：US20170161200A1

公开(公告)日：2017-06-08

申请号：US15424688

申请日：2017-02-03

Applicant: International Business Machines Corporation

Inventor： Philip Heidelberger ,  Hillery C. Hunter ,  James A. Kahle ,  Ravi Nair

IPC: G06F12/0888 ,  G06F12/126

CPC classification number: G06F12/0888 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/604

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

公开(公告)号：US20160378367A1

公开(公告)日：2016-12-29

申请号：US14749680

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Chen-Yong Cher ,  Ravi Nair

IPC: G06F3/06

CPC classification number: G06F9/30043 ,  G06F9/3863 ,  G06F11/00 ,  G06F11/30

Abstract: An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

Abstract translation: 一方面包括接收包括存储器地址和写数据的写请求。 从存储器地址的存储器位置读取存储的数据。 基于确定存储器位置未被修改，将存储的数据与写入数据进行比较。 基于与写入数据匹配的存储数据，写入请求完成，而不将写入数据写入存储器，并且在静默存储位图中设置相应的静默存储位。 基于与写入数据不匹配的存储数据，将写入数据写入存储器位置，无声存储位被复位并且相应的修改位被置位。 为应用程序和操作系统中的至少一个提供对静默存储位图的访问。

公开(公告)号：US20160364364A1

公开(公告)日：2016-12-15

申请号：US14948656

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F15/173 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F13/362 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/17337

Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.

公开(公告)号：US20160364352A1

公开(公告)日：2016-12-15

申请号：US14739014

申请日：2015-06-15

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/17337

Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.

Abstract translation: 提供处理元件之间数据的直接通信。 一个方面包括由第一处理单元通过一个处理间链接总线发送数据。 数据经由数据交换部件发往另一个处理元件，该数据交换部件经由设置在第一处理元件和第二处理元件的相应复用器之间的通信线路耦合在第一处理元件和第二处理元件之间。 另一方面包括由数据交换组件确定数据是否已经在数据交换元件处被接收。 如果是这样，则在数据交换组件的寄存器中设置指示符，并将数据转发到另一处理单元。 设置指示灯使第一个处理元件停止。 如果没有接收到数据，则在数据交换组件等待接收数据的同时处理元件停止。

公开(公告)号：US20160363916A1

公开(公告)日：2016-12-15

申请号：US14736758

申请日：2015-06-11

Applicant: International Business Machines Corporation

Inventor： Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Bryan S. Rosenburg

IPC: G05B15/02

CPC classification number: G05B15/02

Abstract: A computer detects a request by a process for access to a shadow control page, wherein the shadow control page allows the process access to one or more devices. The computer assigns the shadow control page and a key to the process associated with the request. The computer detects a request by the process via the assigned shadow control page for creation of a subset of devices from the one or more devices. The computer inputs information detailing an association between the subset of devices and the assigned key into a subset definition table, wherein the subset definition table includes one or more keys and one or more corresponding subsets.

Abstract translation: 计算机检测进程访问影子控制页面的请求，其中阴影控制页面允许对一个或多个设备的进程访问。 计算机将阴影控制页面和一个密钥分配给与请求相关联的进程。 计算机通过所分配的影子控制页面检测该过程的请求，以从一个或多个设备创建设备子集。 计算机将详细描述设备子集与所分配的密钥之间的关联的信息输入到子集定义表中，其中子集定义表包括一个或多个密钥和一个或多个相应的子集。

公开(公告)号：US20160313947A1

公开(公告)日：2016-10-27

申请号：US15198868

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/18

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Abstract translation: 根据一个实施例，一种用于存储器设备中的业务优先级排序的方法包括：将存储器设备中的处理元件中包含优先级值的存储器访问请求发送到存储器设备中的交叉连接。 存储器访问请求通过交叉开关互连路由到与存储器访问请求相关联的存储器设备中的存储器控​​制器。 存储器访问请求在存储器控制器处被接收。 将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求。 存储器控制器基于最高优先级的存储器访问请求来执行下一个存储器访问请求。

公开(公告)号：US20160292128A1

公开(公告)日：2016-10-06

申请号：US14672568

申请日：2015-03-30

Applicant: International Business Machines Corporation

Inventor： Constantinos Evangelinos ,  Changhoan Kim ,  Ravi Nair

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8076 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/3851 ,  G06F15/8053 ,  G06F15/8084

Abstract: In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

公开(公告)号：US09218291B2

公开(公告)日：2015-12-22

申请号：US13950371

申请日：2013-07-25

Applicant: International Business Machines Corporation

Inventor： Philip Heidelberger ,  Hillery C. Hunter ,  James A. Kahle ,  Ravi Nair

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/604

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract translation: 一种用于在存储器系统中实现存储器层级放置决策的方法，系统和存储器控制器，包括将到达数据直接路由到主存储器系统中，并且将数据或计算结果选择性地注入计算机系统中的处理器高速缓存。 存储器控制器或存储器系统中的处理元件选择性地将数据放置到存储器层级的其他级别中。 注入层次结构的决定可以通过来自输入输出（IO）设备的数据到来自计算或来自存储器内处理元件的指令来触发。

公开(公告)号：US09110734B2

公开(公告)日：2015-08-18

申请号：US13674224

申请日：2012-11-12

Applicant: International Business Machines Corporation

Inventor： Hans M. Jacobson ,  Ravi Nair ,  John K. P. O'Brien ,  Zehra N. Sura

IPC: G06F9/50 ,  G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/45

CPC classification number: G06F9/5094 ,  G06F1/329 ,  G06F8/41 ,  G06F9/46 ,  G06F9/4893 ,  Y02D10/24

Abstract: A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into a discrete number of power tokens. Each of the power tokens has an equal value of units of power. The method also includes determining a power requirement for executing a code segment on a processing element of the heterogeneous processing system. The determining is based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, at least one of the power tokens to satisfy the power requirement.

Abstract translation: 异构处理系统包括用于在异构处理系统中执行功率约束代码生成和调度工作的编译器。 编译器生成可由计算机执行的源代码。 编译器执行一个方法。 该方法包括将异构处理系统的功率预算分成离散数量的功率令牌。 每个功率令牌具有相等的功率单位。 该方法还包括确定在异构处理系统的处理元件上执行代码段的功率需求。 该确定基于处理元件和代码段的特性。 该方法还包括在运行时向处理元件分配至少一个功率令牌以满足功率需求。