公开(公告)号：US10957582B2

公开(公告)日：2021-03-23

申请号：US16451278

申请日：2019-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/31 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532 ,  H01L21/82 ,  H01L21/027 ,  H01L21/3105

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

公开(公告)号：US20200251386A1

公开(公告)日：2020-08-06

申请号：US16857408

申请日：2020-04-24

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Terry A. Spooner ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

公开(公告)号：US10658235B2

公开(公告)日：2020-05-19

申请号：US16014780

申请日：2018-06-21

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Terry A. Spooner ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

公开(公告)号：US20190393085A1

公开(公告)日：2019-12-26

申请号：US16014780

申请日：2018-06-21

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Terry A. Spooner ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

公开(公告)号：US10256185B2

公开(公告)日：2019-04-09

申请号：US15793020

申请日：2017-10-25

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/3065 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.

公开(公告)号：US20180261543A1

公开(公告)日：2018-09-13

申请号：US15978829

申请日：2018-05-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Baozhen Li ,  Kirk D. Peterson ,  Terry A. Spooner ,  Junli Wang

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/28562 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dieletric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

公开(公告)号：US20180158731A1

公开(公告)日：2018-06-07

申请号：US15889248

申请日：2018-02-06

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Baozhen Li ,  Kirk D. Peterson ,  John E. Sheets, II ,  Terry A. Spooner

IPC: H01L21/768 ,  G06F17/50 ,  H01L21/66

Abstract: A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.

公开(公告)号：US09953864B2

公开(公告)日：2018-04-24

申请号：US15251403

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76825 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.

公开(公告)号：US20180090436A1

公开(公告)日：2018-03-29

申请号：US15793020

申请日：2017-10-25

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wei Wang ,  Chi-Chao Yang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/3065 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295

Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.

公开(公告)号：US20180082945A1

公开(公告)日：2018-03-22

申请号：US15444933

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih -Chao Yang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: Conductive contacts include a first conductor disposed within a first dielectric layer, the first conductor having a recessed area in least one surface. A second dielectric layer is formed over the first dielectric layer, comprising a trench positioned over the first conductor. A second conductor is formed in the trench and the recessed area to form a conductive contact with the first conductor.