公开(公告)号：US11133216B2

公开(公告)日：2021-09-28

申请号：US15995768

申请日：2018-06-01

申请人： International Business Machines Corporation

发明人： Hsueh-Chung Chen ,  Roger A. Quon ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

摘要： A nitridation treatment method is provided. The nitridation treatment method includes executing a nitridation treatment with respect to a hydrophobic surface defining an interconnect trench to convert the hydrophobic surface to a hydrophilic surface. The nitridation treatment method further includes depositing a seed layer including a conductive material and manganese on the hydrophilic surface. The nitridation treatment method also includes thermally driving all the manganese out of the seed layer to form a diffusion barrier including manganese at the hydrophilic surface. In addition, the nitridation treatment method includes filling remaining space in the interconnect trench with the conductive material to form an interconnect.

公开(公告)号：US10957583B2

公开(公告)日：2021-03-23

申请号：US16553342

申请日：2019-08-28

申请人： International Business Machines Corporation

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Sivananda K. Kanakasabapathy ,  Yann A. M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/033 ,  H01L21/027

摘要： An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a β line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a γ line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an α line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a βγβ jog; a βαβ jog; an αβγ jog; a γβα jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

公开(公告)号：US20200111699A1

公开(公告)日：2020-04-09

申请号：US16151390

申请日：2018-10-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Cornelius B. Peethala ,  Raghuveer R. Patlolla ,  Chih-Chao Yang ,  Roger A. Quon

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

摘要： A method for back end of line (BEOL) integration for one or more interconnects includes forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric, forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers to remove portions of the diffusion barrier layer along the interlevel dielectric.

公开(公告)号：US10249532B2

公开(公告)日：2019-04-02

申请号：US15443583

申请日：2017-02-27

申请人： International Business Machines Corporation

发明人： Roger A. Quon ,  Michael Rizzolo ,  Chih-Chao Yang

IPC分类号： C23C16/50 ,  H01L21/768 ,  C23C16/56 ,  C23C16/455 ,  C23C16/52 ,  C23C16/34 ,  C23C16/06 ,  C23C14/58 ,  H01L21/67

摘要： Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate microstructures of metallic interconnect structures. For example, an apparatus includes a single platform semiconductor processing chamber having first and second sub-chambers. The first sub-chamber is configured to receive a semiconductor substrate comprising a metallization layer formed on a dielectric layer, wherein a portion of the metallization layer is disposed within an opening etched in the dielectric layer, and to form a stress control layer on the metallization layer. The second sub-chamber comprises a programmable hot plate which is configured to perform a thermal anneal process to modulate a microstructure of the metallization layer while the stress control layer is disposed on the metallization layer, and without an air break between the process modules of forming the stress control layer and performing the thermal anneal process.

公开(公告)号：US09934970B1

公开(公告)日：2018-04-03

申请号：US15403371

申请日：2017-01-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L29/40 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/31 ,  H01L21/027 ,  H01L45/00 ,  H01L21/28 ,  H01L51/00

CPC分类号： H01L21/0337 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L45/1675 ,  H01L51/0018 ,  H01L2224/0362 ,  H01L2224/11622

摘要： A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US09911647B2

公开(公告)日：2018-03-06

申请号：US15677447

申请日：2017-08-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Anuja E. DeSilva ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Yann A. M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76897 ,  H01L23/528

摘要： A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.

公开(公告)号：US20170352585A1

公开(公告)日：2017-12-07

申请号：US15172265

申请日：2016-06-03

申请人： International Business Machines Corporation

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Sivananda K. Kanakasabapathy ,  Yann A.M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/76816 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02697 ,  H01L21/027 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266

摘要： An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a β line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a γ line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an α line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a βγβ jog; a βαβ jog; an αβγ jog; a γβα jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

公开(公告)号：US09779944B1

公开(公告)日：2017-10-03

申请号：US15263959

申请日：2016-09-13

申请人： International Business Machines Corporation

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Yann A. M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/311 ,  H01L21/033

CPC分类号： H01L21/31144 ,  H01L21/0337

摘要： A method for manufacturing a semiconductor device includes forming a plurality of mandrels on a dielectric layer, conformally depositing a spacer layer on the plurality of mandrels, removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels, removing the at least one of the plurality of mandrels to create at least one opening, and filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer.

公开(公告)号：US10256185B2

公开(公告)日：2019-04-09

申请号：US15793020

申请日：2017-10-25

申请人： International Business Machines Corporation

发明人： Lawrence A. Clevenger ,  Roger A. Quon ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC分类号： H01L23/522 ,  H01L21/3065 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

摘要： A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.

公开(公告)号：US20180197738A1

公开(公告)日：2018-07-12

申请号：US15786090

申请日：2017-10-17

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L45/00 ,  H01L21/027 ,  H01L21/31 ,  H01L21/28 ,  H01L51/00

CPC分类号： H01L21/0337 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L45/1675 ,  H01L51/0018 ,  H01L2224/0362 ,  H01L2224/11622

摘要： A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.