公开(公告)号：US20240015417A1

公开(公告)日：2024-01-11

申请号：US17857615

申请日：2022-07-05

Applicant: Infineon Technologies AG

Inventor： Wolfgang Budde ,  Jens de Bock ,  Daniel Domes ,  Andreas Lenniger ,  Bjoern Rentemeister ,  Stefan Hubert Schmies ,  Andreas Vetter

IPC: H04Q9/00

CPC classification number: H04Q9/00 ,  H04Q2209/84 ,  H04Q2209/10

Abstract: An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.

公开(公告)号：US11770119B2

公开(公告)日：2023-09-26

申请号：US17852785

申请日：2022-06-29

Applicant: Infineon Technologies AG

Inventor： Zheming Li ,  Mark-Matthias Bakran ,  Daniel Domes ,  Robert Maier ,  Franz-Josef Niedernostheide

IPC: H03K17/042 ,  H03K17/04

CPC classification number: H03K17/0406 ,  H03K17/042 ,  H03K17/04206 ,  H03K2217/0027

Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

公开(公告)号：US11444613B1

公开(公告)日：2022-09-13

申请号：US17372913

申请日：2021-07-12

Applicant: Infineon Technologies AG

Inventor： Zheming Li ,  Mark-Matthias Bakran ,  Daniel Domes ,  Robert Maier ,  Franz-Josef Niedernostheide

IPC: H03K17/04 ,  H03K17/042

Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

公开(公告)号：US20210043605A1

公开(公告)日：2021-02-11

申请号：US16939130

申请日：2020-07-27

Applicant: Infineon Technologies AG

Inventor： Christian Robert Mueller ,  Andressa Colvero Schittler ,  Daniel Domes ,  Andre Lenze

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L23/64 ,  H01L23/049

Abstract: A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

公开(公告)号：US20180308827A1

公开(公告)日：2018-10-25

申请号：US15957561

申请日：2018-04-19

Applicant: Infineon Technologies AG

Inventor： Matthias Wissen ,  Daniel Domes ,  Andreas Groove

IPC: H01L25/10 ,  H01L23/492 ,  H01L23/52 ,  H01L23/367

CPC classification number: H01L25/105 ,  H01L23/3675 ,  H01L23/4922 ,  H01L23/52 ,  H01L25/115 ,  H01L25/117 ,  H05K1/0216

Abstract: A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another.

公开(公告)号：US20160094216A1

公开(公告)日：2016-03-31

申请号：US14862582

申请日：2015-09-23

Applicant: Infineon Technologies AG

Inventor： Daniel Domes

IPC: H03K17/567

CPC classification number: H03K17/567 ,  H03K2217/0036

Abstract: A drive circuit includes a first output node for connection to the control electrode of the semiconductor switch, a voltage supply circuit, and a first switching stage connected to the voltage supply and a second switching stage connected to the voltage supply. A first resistor network is connected between the first switching stage and the first output node. A second resistor network is connected between the second switching stage and the first output node. A control logic is designed to generate control signals for the guiding of the first switching stage and the second switching stage in such a way that in a first operating mode of the semiconductor switch the semiconductor switch is driven only via the first resistor network, and in a second operating mode of the semiconductor switch the semiconductor switch is driven only via the second resistor network or both resistor networks.

Abstract translation: 驱动电路包括用于连接到半导体开关的控制电极的第一输出节点，电压供应电路和连接到电压源的第一开关级和连接到电压源的第二开关级。 第一电阻网络连接在第一开关级与第一输出节点之间。 第二电阻网络连接在第二开关级与第一输出节点之间。 控制逻辑被设计为产生用于引导第一开关级和第二开关级的控制信号，使得在半导体开关的第一操作模式中半导体开关仅通过第一电阻器网络驱动，并且在 半导体开关的第二操作模式仅通过第二电阻网络或两个电阻网络驱动半导体开关。