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    CONSOLIDATION OF INTERRUPT LOST EVENTS IN MULTI-LEVEL INTERRUPT SYSTEM
    21.
    发明申请
    CONSOLIDATION OF INTERRUPT LOST EVENTS IN MULTI-LEVEL INTERRUPT SYSTEM 有权

    公开(公告)号：US20250165278A1

    公开(公告)日：2025-05-22

    申请号：US18597086

    申请日：2024-03-06

    Applicant: Infineon Technologies AG

    Inventor： Frank Hellwig

    IPC: G06F9/48 ,  G06F9/30

    Abstract: Systems, methods, and circuitries are provided for detecting lost interrupt events in a reduced instruction set computer-V (RISC-V) architecture. An example architecture includes an advanced platform level interrupt controller (APLIC) and an incoming message signaled interrupt (MSI) controller (IMSIC) coupled to the APLIC. The APLIC includes a plurality of respective vectors connected to respective external interrupt inputs, wherein each vector is mapped to an interrupt priority and each vector comprises a vector interrupt lost (IL) bit. The IMSIC is configured to receive MSI from the APLIC and to maintain an interrupt file that includes a set of a set of interrupt lost (IL) bits indexed by interrupt priority.

    SYSTEMS, DEVICES, AND METHODS FOR DYNAMIC ALLOCATION
    22.
    发明公开
    SYSTEMS, DEVICES, AND METHODS FOR DYNAMIC ALLOCATION 审中-公开

    公开(公告)号：US20230161862A1

    公开(公告)日：2023-05-25

    申请号：US17981583

    申请日：2022-11-07

    Applicant: Infineon Technologies AG

    Inventor： Sandeep Vangipuram ,  Glenn Farrall ,  Albrecht Mayer ,  Frank Hellwig

    IPC: G06F21/44

    CPC classification number: G06F21/44

    Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

    Resource protection
    23.
    发明授权
    Resource protection 有权

    公开(公告)号：US11288404B2

    公开(公告)日：2022-03-29

    申请号：US16441227

    申请日：2019-06-14

    Applicant: Infineon Technologies AG

    Inventor： Albrecht Mayer ,  Glenn Ashley Farrall ,  Frank Hellwig

    IPC: G06F21/74

    Abstract: A System on Chip (SoC), including a plurality of processor cores including a secure master, which is configured to run security software, and a non-secure master, which is configured to run non-security software; a resource configured to be shared by the secure master and the non-secure master; and a state machine configured to protect the resource by allowing only the secure master to transition the resource to a particular state of the state machine, and allowing only the non-secure master to transition the resource to another particular state of the state machine.

    Bus system and method of protected memory access
    27.
    发明授权
    Bus system and method of protected memory access 有权

    公开(公告)号：US09703728B2

    公开(公告)日：2017-07-11

    申请号：US14494078

    申请日：2014-09-23

    Applicant: Infineon Technologies AG

    Inventor： Frank Hellwig ,  Simon Cottam

    IPC: G06F12/14 ,  G06F13/28

    CPC classification number: G06F12/1458 ,  G06F13/28 ,  G06F2212/1052

    Abstract: A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region.

    Conditional links for direct memory access controllers
    28.
    发明授权
    Conditional links for direct memory access controllers 有权
    直接内存访问控制器的条件链接

    公开(公告)号：US09569384B2

    公开(公告)日：2017-02-14

    申请号：US13803811

    申请日：2013-03-14

    Applicant: Infineon Technologies AG

    Inventor： Frank Hellwig ,  Simon Cottam ,  Harald Zweck

    IPC: G06F13/28

    CPC classification number: G06F13/28

    Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.

    Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括具有系统总线接口并被配置为经由系统总线接口从存储器位置读取模式的总线控制器。 图案比较逻辑将读取图案与至少一个预定图案进行比较。 如果读取模式与预定模式不同，则控制逻辑引起总线控制器处理系统总线接口上的第一条件链路，并且如果读取模式与系统总线接口不同，则总线控制器通过系统总线接口处理第二条件链路 预定模式。

    DMA integrity checker
    29.
    发明授权
    DMA integrity checker 有权
    DMA完整性检查器

    公开(公告)号：US08996926B2

    公开(公告)日：2015-03-31

    申请号：US13651775

    申请日：2012-10-15

    Applicant: Infineon Technologies AG

    Inventor： Simon Brewerton ,  Simon Cottam ,  Frank Hellwig

    IPC: G06F11/00 ,  G06F11/10

    CPC classification number: G06F11/1048

    Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

    Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括一组事务控制寄存器，用于接收共同描述要由DMA控制器处理的数据传输的事务控制集合的序列。 总线控制器读取和写入存储器，而DMA控制器执行第一事务控制集以完成事务控制集序列中描述的部分数据传输。 完整性检查器基于在执行第一事务控制集期间由DMA控制器实际处理的数据或地址来确定实际的错误检测码。 完整性检查器还基于实际错误检测码是否与包含在事务控制集合的顺序的第二事务控制集中的期望错误检测码相同来选择性地标记错误。

    PROCESSING OF INTERRUPTS
    30.
    发明公开
    PROCESSING OF INTERRUPTS 审中-公开

    公开(公告)号：US20230342187A1

    公开(公告)日：2023-10-26

    申请号：US18302053

    申请日：2023-04-18

    Applicant: Infineon Technologies AG

    Inventor： Frank Hellwig ,  Sandeep Vangipuram

    IPC: G06F9/48 ,  G06F13/28

    CPC classification number: G06F9/4818 ,  G06F13/28

    Abstract: It is suggested to process an interrupt event as follows: (i) receiving an interrupt event at a service request node; (ii) providing, by the service request node, an interrupt service request based on the interrupt event, and a security information; and (iii) forwarding the interrupt service request to an interrupt service provider.

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