公开(公告)号：US20220399342A1

公开(公告)日：2022-12-15

申请号：US17347735

申请日：2021-06-15

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Wilfred Gomes ,  Mauro J. Kobrinsky ,  Van H. Le

IPC分类号： H01L27/108 ,  H01L27/092 ,  H01L29/66

摘要： Described herein are three-dimensional transistors with a recessed gate, and IC devices including such three-dimensional transistors with recessed gates. The transistor includes a channel material having a recess. The channel material is formed over a support structure, and source/drain regions are formed in or on the channel material, e.g., one either side of the recess. A gate stack extends through the recess. The distance between the gate stack and the support structure is smaller than the distance between one of the source/drain regions and the support structure. This arrangement increases the channel length relative to prior art transistors, reducing leakage.

公开(公告)号：US20220399310A1

公开(公告)日：2022-12-15

申请号：US17345369

申请日：2021-06-11

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Wilfred Gomes ,  Mauro J. Kobrinsky ,  Doug B. Ingerly ,  Van H. Le

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

摘要： Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

公开(公告)号：US11522059B2

公开(公告)日：2022-12-06

申请号：US15899590

申请日：2018-02-20

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert W. Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC分类号： H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/45 ,  H01L23/29 ,  H01L29/24 ,  H01L29/22

摘要： Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US11444204B2

公开(公告)日：2022-09-13

申请号：US15939081

申请日：2018-03-28

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Sean T. Ma ,  Jack Kavalieros ,  Benjamin Chu-Kung

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12

摘要： Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.

公开(公告)号：US11374056B2

公开(公告)日：2022-06-28

申请号：US16630924

申请日：2017-09-14

申请人： Intel Corporation

发明人： Elijah V. Karpov ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Abhishek A. Sharma

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L45/00

摘要： Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur.

公开(公告)号：US20220181256A1

公开(公告)日：2022-06-09

申请号：US17114537

申请日：2020-12-08

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H01L23/48

摘要： Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US11309400B2

公开(公告)日：2022-04-19

申请号：US16650153

申请日：2018-01-12

申请人： INTEL CORPORATION

发明人： Seung Hoon Sung ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06

摘要： Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

公开(公告)号：US11222921B2

公开(公告)日：2022-01-11

申请号：US16635111

申请日：2017-08-29

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00

摘要： Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.

公开(公告)号：US11152514B2

公开(公告)日：2021-10-19

申请号：US16640340

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Van H. Le ,  Abhishek A. Sharma ,  Gilbert Dewey ,  Kent Millard ,  Jack Kavalieros ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Justin R. Weber ,  Tahir Ghani ,  Li Huey Tan ,  Kevin Lin

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267

摘要： Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

公开(公告)号：US11139296B2

公开(公告)日：2021-10-05

申请号：US15941384

申请日：2018-03-30

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady ,  Ravi Pillarisetty

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/02

摘要： Techniques and mechanisms for providing a space efficient complementary metal-oxide-semiconductor (CMOS) circuit. In an embodiment, a p-type transistor of a circuit is to conduct current in a direction parallel to a surface of a semiconductor substrate, wherein an n-type thin film transistor (TFT) of the circuit is to conduct current in a direction which is orthogonal to the surface. A first interconnect is directly coupled to each of the two transistors, wherein the first interconnect, a high mobility channel structure of the n-type TFT, and a source or drain of the p-type transistor are on the same line of direction. A second interconnect comprises a conductive path which extends to respective gates of the p-type transistor and the n-type TFT, wherein the conductive path is limited to a region over a footprint of the p-type transistor. In another embodiment, functionality of a logical inverter is provided with the circuit.