公开(公告)号：US20210224202A1

公开(公告)日：2021-07-22

申请号：US17222722

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Hormuzd M. Khosravi ,  Gideon Gerzon ,  Barry E. Huntley ,  Gilbert Neiger ,  Ido Ouziel ,  Baiju Patel ,  Ravi L. Sahita ,  Amy L. Santoni ,  Ioannis T. Schoinas

IPC: G06F12/14 ,  H04L29/06 ,  H04L9/06 ,  H04L9/08

Abstract: In one embodiment, an apparatus comprises a processor to execute instruction(s), wherein the instructions comprise a memory access operation associated with a memory location of a memory. The apparatus further comprises a memory encryption controller to: identify the memory access operation; determine that the memory location is associated with a protected domain, wherein the protected domain is associated with a protected memory region of the memory, and wherein the protected domain is identified from a plurality of protected domains associated with a plurality of protected memory regions of the memory; identify an encryption key associated with the protected domain; perform a cryptography operation on data associated with the memory access operation, wherein the cryptography operation is performed based on the encryption key associated with the protected domain; and return a result of the cryptography operation, wherein the result is to be used for the memory access operation.

公开(公告)号：US10859627B2

公开(公告)日：2020-12-08

申请号：US15636762

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

IPC: G01R31/317 ,  H04L12/26 ,  G01R31/26 ,  H04L12/24 ,  G01R31/28

Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

公开(公告)号：US20190324918A1

公开(公告)日：2019-10-24

申请号：US16402442

申请日：2019-05-03

Applicant: INTEL CORPORATION

Inventor： Krystof C. Zmudzinski ,  Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Ilya Alexandrovich ,  Ittai Anati ,  Wesley H. Smith ,  Michael Goldsmith

IPC: G06F12/1009 ,  G06F12/1036 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/14 ,  G06F9/455

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

公开(公告)号：US20190007200A1

公开(公告)日：2019-01-03

申请号：US15638162

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Neel Shah ,  Kirk S. Yap ,  Amy L. Santoni ,  Michael Neve de Mevergnies ,  Oscar Mendoza ,  Sreejit Chakravarty ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici

IPC: H04L9/08 ,  G01R31/317 ,  G01R31/26 ,  H04L9/06

Abstract: A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.

公开(公告)号：US09612930B2

公开(公告)日：2017-04-04

申请号：US14737768

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22 ,  G06F11/14

CPC classification number: G06F11/2635 ,  G06F11/1417 ,  G06F11/1433 ,  G06F11/2242 ,  G06F11/2268 ,  G06F11/27

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.