中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.025 seconds)

    PACKAGE PIN PATTERN FOR DEVICE-TO-DEVICE CONNECTION
    21.
    发明申请
    PACKAGE PIN PATTERN FOR DEVICE-TO-DEVICE CONNECTION 有权

    公开(公告)号：US20210074333A1

    公开(公告)日：2021-03-11

    申请号：US17086220

    申请日：2020-10-30

    Applicant: Intel Corporation

    Inventor： Chong J. ZHAO ,  James A. McCALL ,  Robert J. FRIAR ,  Yidnekachew S. MEKONNEN ,  San K. CHHAY

    IPC: G11C5/06 ,  G11C8/18 ,  H05K5/02

    Abstract: Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.

    APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE
    22.
    发明申请
    APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE 审中-公开

    公开(公告)号：US20190139592A1

    公开(公告)日：2019-05-09

    申请号：US16177284

    申请日：2018-10-31

    Applicant: Intel Corporation

    Inventor： Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Ge Chang

    IPC: G11C11/4074 ,  G11C11/408 ,  G11C7/10 ,  G11C8/06 ,  G06F3/06 ,  G06F13/16

    Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

    DUAL IN-LINE MEMORY MODULE (DIMM) SOLUTION THAT INCLUDES FLEXIBLE TRANSMISSION LINES
    26.
    发明公开
    DUAL IN-LINE MEMORY MODULE (DIMM) SOLUTION THAT INCLUDES FLEXIBLE TRANSMISSION LINES 审中-公开

    公开(公告)号：US20240237193A1

    公开(公告)日：2024-07-11

    申请号：US18618075

    申请日：2024-03-27

    Applicant: Intel Corporation

    Inventor： Yi HUANG ,  Xiaoning YE ,  Kai XIAO ,  James A. McCALL ,  Yanjie ZHU

    IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14

    CPC classification number: H05K1/0253 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/10189

    Abstract: An apparatus is described. The apparatus includes a memory module. The memory module includes a first printed circuit board having a first transmission line. The first printed circuit board has memory chips disposed thereon. The memory module includes a second printed board having a second transmission line that is coupled to the first transmission line to form a signal path through the first and second printed circuit boards. The second printed circuit board has greater flexibility than the first printed circuit board. The memory module includes a connector to align an I/O that is coupled to the second transmission line with a corresponding I/O that is associated with a motherboard that is to send and/or receive a signal to and/or from the signal path.

    MULTI-CHANNEL MEMORY MODULE
    27.
    发明申请
    MULTI-CHANNEL MEMORY MODULE 有权

    公开(公告)号：US20230044892A1

    公开(公告)日：2023-02-09

    申请号：US17969518

    申请日：2022-10-19

    Applicant: Intel Corporation

    Inventor： Xiang LI ,  Saravanan SETHURAMAN ,  George VERGIS ,  James A. McCALL

    IPC: H05K1/11 ,  H01L25/18 ,  H05K1/18

    Abstract: According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.

    SHIELDED SOCKET PIN FOR DEVICE-TO-DEVICE CONNECTION
    28.
    发明申请
    SHIELDED SOCKET PIN FOR DEVICE-TO-DEVICE CONNECTION 有权

    公开(公告)号：US20220263262A1

    公开(公告)日：2022-08-18

    申请号：US17737243

    申请日：2022-05-05

    Applicant: Intel Corporation

    Inventor： Landon HANKS ,  Xiang LI ,  George VERGIS ,  James A. McCALL

    IPC: H01R13/24 ,  H01R13/652 ,  H01R13/04 ,  H01R12/71

    Abstract: Examples described herein relate to a system that includes: a first signal pin and a first ground pin adjacent to the first signal pin. In some examples, the first signal pin comprises a first portion, a second portion, and a third portion. In some examples, the first ground pin comprises a first portion, a second portion, and a third portion, the second portion of the first signal pin comprises a vertical mount, the second portion of the first ground pin comprises a vertical mount, and the second portion of the first signal pin and the second portion of the first ground pin are arranged proximate one another.

    STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I/OS)
    30.
    发明申请
    STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I/OS) 有权

    公开(公告)号：US20210335393A1

    公开(公告)日：2021-10-28

    申请号：US17372298

    申请日：2021-07-09

    Applicant: Intel Corporation

    Inventor： Chong J. ZHAO ,  Shigeki TOMISHIMA ,  Kuljit S. BAINS ,  James A. McCALL ,  Dimitrios ZIAKAS

    IPC: G11C5/06

    Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

Patent Agency Ranking