公开(公告)号：US20240220622A1

公开(公告)日：2024-07-04

申请号：US18149055

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Eric Geisler ,  Rupin H. Vakharwala ,  Michael Prinke ,  David Koufaty

IPC: G06F21/57

CPC classification number: G06F21/57 ,  G06F2221/033

Abstract: Circuitry and methods for implementing address translation extensions for confidential computing hosts are described. In certain examples, a system includes a hardware processor core to implement a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory; an input/output device coupled to the hardware processor core; and input/output memory management unit (IOMMU) circuitry comprising trusted direct memory access translation data and coupled between the hardware processor core and the input/output device, wherein the IOMMU circuitry is to, for a request from the input/output device for a direct memory access of a protected memory of a trust domain: in response to a field in the request being set to indicate the input/output device is in a trusted computing base of the trust domain and an entry in the trusted direct memory access translation data being set into an active state by the trust domain manager, allow the direct memory access by the input/output device.

公开(公告)号：US11726927B2

公开(公告)日：2023-08-15

申请号：US17827458

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1045 ,  G06F13/42

CPC classification number: G06F13/161 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1063 ,  G06F13/1663 ,  G06F13/4282 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2213/0026

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

公开(公告)号：US20230035420A1

公开(公告)日：2023-02-02

申请号：US17955353

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20220100911A1

公开(公告)日：2022-03-31

申请号：US17548170

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Anna Trikalinou ,  Abhishek Basak ,  Rupin H. Vakharwala ,  Utkarsh Y. Kakaiya

IPC: G06F21/83 ,  G06F21/62 ,  G06F21/78

Abstract: In one embodiment, a read request is received from a peripheral device across an interconnect, with the read request including a process identifier and an encrypted virtual address. One or more keys are obtained based on the process identifier of the read request, and the encrypted virtual address of the read request is decrypted based on the one or more keys to obtain an unencrypted virtual address. Encrypted data is retrieved from memory based on the unencrypted virtual address, and the encrypted data is decrypted based on the one or more keys to obtain plaintext data. The plaintext data is transmitted to the peripheral device across the interconnect.

公开(公告)号：US10970238B2

公开(公告)日：2021-04-06

申请号：US16566865

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US10936490B2

公开(公告)日：2021-03-02

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/08 ,  G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US20200004703A1

公开(公告)日：2020-01-02

申请号：US16566865

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20180137069A1

公开(公告)日：2018-05-17

申请号：US15350998

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Rupin H. Vakharwala ,  Camron B. Rust

IPC: G06F13/28 ,  G06F9/44

CPC classification number: G06F13/28 ,  G06F9/4401 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2212/1041 ,  G06F2212/15 ,  G06F2212/502 ,  G06F2212/651

Abstract: Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.

公开(公告)号：US09954792B2

公开(公告)日：2018-04-24

申请号：US14578429

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Kevin B. Theobald ,  Rupin H. Vakharwala ,  Robert J. Toepfer ,  Erik G. Hallnor ,  Robert P. Adler

IPC: H04L12/28 ,  H04L12/801 ,  H04L12/46 ,  H04L12/707 ,  H04L12/925 ,  H04L12/911

CPC classification number: H04L47/39 ,  H04L12/4641 ,  H04L45/24 ,  H04L47/722 ,  H04L47/726 ,  H04L47/821

Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.