公开(公告)号：US20220237033A1

公开(公告)日：2022-07-28

申请号：US17666366

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Evan Custodio ,  Francesc Guim Bernat ,  Suraj Prabhakaran ,  Trevor Cooper ,  Ned M. Smith ,  Kshitij Doshi ,  Petar Torre

IPC: G06F9/50

Abstract: Technologies for migrating data between edge accelerators hosted on different edge locations include a device hosted on a present edge location. The device includes one or more processors to: receive a workload from a requesting device, determine one or more accelerator devices hosted on the present edge location to perform the workload, and transmit the workload to the one or more accelerator devices to process the workload. The one or more processor is further to determine whether to perform data migration from the one or more accelerator devices to one or more different edge accelerator devices hosted on a different edge location, and send, in response to a determination to perform the data migration, a request to the one or more accelerator devices on the present edge location for transformed workload data to be processed by the one or more different edge accelerator devices.

公开(公告)号：US20220222274A1

公开(公告)日：2022-07-14

申请号：US17580436

申请日：2022-01-20

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Suraj Prabhakaran ,  Ramanathan Sethuraman ,  Timothy Verrall ,  Ned Smith

IPC: G06F16/27 ,  G06F3/06

Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.

公开(公告)号：US11269801B2

公开(公告)日：2022-03-08

申请号：US17125439

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Da-Ming Chiang ,  Kshitij A. Doshi ,  Suraj Prabhakaran ,  Mark A. Schmisseur

IPC: G06F13/40 ,  G06F13/362 ,  G06N3/04 ,  G06F13/42 ,  G06F9/455 ,  G06N3/08

Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

公开(公告)号：US11250336B2

公开(公告)日：2022-02-15

申请号：US15857087

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Suraj Prabhakaran ,  Kshitij Arun Doshi ,  Da-Ming Chiang ,  Joe Cahill

IPC: G06N5/04

Abstract: Various systems and methods of initiating and performing contextualized AI inferencing, are described herein. In an example, operations performed with a gateway computing device to invoke an inferencing model include receiving and processing a request for an inferencing operation, selecting an implementation of the inferencing model on a remote service based on a model specification and contextual data from the edge device, and executing the selected implementation of the inferencing model, such that results from the inferencing model are provided back to the edge device. Also in an example, operations performed with an edge computing device to request an inferencing model include collecting contextual data, generating an inferencing request, transmitting the inference request to a gateway device, and receiving and processing the results of execution. Further techniques for implementing a registration of the inference model, and invoking particular variants of an inference model, are also described.

公开(公告)号：US11095618B2

公开(公告)日：2021-08-17

申请号：US15941724

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Francesc Cesc Guim Bernat ,  Suraj Prabhakaran

IPC: H04L29/06 ,  G06N3/08 ,  G06N3/04 ,  G06F21/14 ,  G06F21/62 ,  H04W12/02 ,  H04L29/08

Abstract: Systems and techniques for AI model and data camouflaging techniques for cloud edge are described herein. In an example, a neural network transformation system is adapted to receive, from a client, camouflaged input data, the camouflaged input data resulting from application of a first encoding transformation to raw input data. The neural network transformation system may be further adapted to use the camouflaged input data as input to a neural network model, the neural network model created using a training data set created by applying the first encoding transformation on training data. The neural network transformation system may be further adapted to receive a result from the neural network model and transmit output data to the client, the output data based on the result.

公开(公告)号：US11025411B2

公开(公告)日：2021-06-01

申请号：US15912733

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Suraj Prabhakaran ,  Kshitij Doshi ,  Timothy Verrall

IPC: H04L29/08 ,  H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L29/06 ,  G06F16/25 ,  G06F16/2453 ,  H04L12/861 ,  G11C8/12 ,  G11C29/02 ,  H04L12/24 ,  G06F30/34 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L12/703 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11 ,  G06F12/0802 ,  G06F12/1045

Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.

公开(公告)号：US20210109785A1

公开(公告)日：2021-04-15

申请号：US17132642

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Suraj Prabhakaran ,  Francesc Guim Bernat

IPC: G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F11/07

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to batch functions. An example apparatus includes a function evaluator to, in response to receiving a function request associated with a function and an input, flag the function for batching, a timing handler to determine a waiting threshold associated with the function, a queue handler to store the function, the input, and the waiting threshold in a queue, and a client interface to, in response to a time duration the function is stored in the queue satisfying the waiting threshold, send the function and the input to a client device to increase throughput to the client device.

公开(公告)号：US20210100070A1

公开(公告)日：2021-04-01

申请号：US16995011

申请日：2020-08-17

Applicant: Intel Corporation

Inventor： Dario Sabella ,  Ned M. Smith ,  Neal Conrad Oliver ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Francesc Guim Bernat ,  Miltiadis Filippou

IPC: H04W88/18 ,  H04W48/08 ,  H04L29/06 ,  H04W4/44 ,  H04W88/16 ,  H04L29/08 ,  H04L12/24 ,  G06F9/455 ,  G06F8/70 ,  H04W12/00

Abstract: Various systems and methods for enhancing a distributed computing environment with multiple edge hosts and user devices, including in multi-access edge computing (MEC) network platforms and settings, are described herein. A device of a lifecycle management (LCM) proxy apparatus obtains a request, from a device application, for an application multiple context of an application. The application multiple context for the application is determined. The request from the device application for the application multiple context for the application is authorized. A device application identifier based on the request is added to the application multiple context. A created response for the device application based on the authorization of the request is transmitted to the device application. The response includes an identifier of the application multiple context.

公开(公告)号：US10936039B2

公开(公告)日：2021-03-02

申请号：US16011842

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Suraj Prabhakaran ,  Timothy Verrall ,  Karthik Kumar ,  Mark A. Schmisseur

IPC: G06F1/3234 ,  H04L29/08 ,  G06F9/50 ,  H04L12/24 ,  G06F1/3293 ,  G06F1/3206 ,  H04L12/26

Abstract: In one embodiment, an apparatus of an edge computing system includes memory that includes instructions and processing circuitry coupled to the memory. The processing circuitry implements the instructions to process a request to execute at least a portion of a workflow on pooled computing resources, the workflow being associated with a particular tenant, determine an amount of power to be allocated to particular resources of the pooled computing resources for execution of the portion of the workflow based on a power budget associated with the tenant and a current power cost, and control allocation of the determined amount of power to the particular resources of the pooled computing resources during execution of the portion of the workflow.

公开(公告)号：US20190394096A1

公开(公告)日：2019-12-26

申请号：US16563175

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Doshi ,  Suraj Prabhakaran ,  Ned M. Smith

IPC: H04L12/24 ,  H04L29/08 ,  H04L12/911 ,  H04L12/66

Abstract: Technologies for batching requests in an edge infrastructure include a compute device including circuitry configured to obtain a request for an operation to be performed at an edge location. The circuitry is also configured to determine, as a function of a parameter of the obtained request, a batch that the obtained request is to be assigned to. The batch includes a one or more requests for operations to be performed at an edge location. The circuitry is also configured to assign the batch to a cloudlet at an edge location. The cloudlet includes a set of resources usable to execute the operations requested in the batch.