公开(公告)号：US20140167221A1

公开(公告)日：2014-06-19

申请号：US13720289

申请日：2012-12-19

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

Inventor： Xiangxin Rui ,  Sergey Barabash

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L28/40 ,  H01L28/56 ,  H01L28/60

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor layer inserted between the dielectric layer and at least one of the two electrode layers. In some embodiments, the dielectric layer may be doped with an oxygen donor dopant. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.

Abstract translation: 降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括形成电容器堆叠，该电容器堆叠包括介于介电层和两个电极层中的至少一个之间的供氧体层。 在一些实施例中，介电层可以掺杂有氧供体掺杂剂。 氧供体材料为介电层提供氧气并降低氧空位的浓度，从而减少漏电流。

公开(公告)号：US20130217202A1

公开(公告)日：2013-08-22

申请号：US13830282

申请日：2013-03-14

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US20130140675A1

公开(公告)日：2013-06-06

申请号：US13738901

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Sandra Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/56 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02304 ,  H01L28/40

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括：形成第一电极层，在第一电极层上形成催化层，任选地退火催化层，在催化层上形成电介质层， 在电介质层上形成第二电极层，并且可选地对电容器堆叠进行退火。 有利地，电极层是TiN，催化剂层是MoO 2-x，其中x在0和2之间，催化层的物理厚度在约0.5nm和约10nm之间，并且电介质层是ZrO 2。

公开(公告)号：US20130037913A1

公开(公告)日：2013-02-14

申请号：US13655653

申请日：2012-10-19

Applicant: INTERMOLECULAR INC.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati KUMAR ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L29/02

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

公开(公告)号：US20160093625A1

公开(公告)日：2016-03-31

申请号：US14502728

申请日：2014-09-30

Applicant: Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Imran Hashim ,  Prashant B. Phatak

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/55

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. The dielectric layer may include zirconium oxide or doped zirconium oxide. In some embodiments, the conductive metal oxide layer includes niobium oxide.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 电介质层可以包括氧化锆或掺杂氧化锆。 在一些实施例中，导电金属氧化物层包括氧化铌。

公开(公告)号：US20150228710A1

公开(公告)日：2015-08-13

申请号：US14177118

申请日：2014-02-10

Applicant: Elpida Memory, Inc ,  Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Hanhong Chen ,  Naonori Fujiwara ,  Imran Hashim ,  Kenichi Koyanagi

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01G4/1236 ,  H01G4/33 ,  H01L27/10805 ,  H01L27/1085 ,  H01L28/56 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (

Abstract translation: 用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料和轻掺杂或非掺杂材料形成多层电介质叠层。 退火步骤后，高掺杂材料将保持无定形（<30％结晶）。 在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。 在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（≥30％结晶）。 高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

公开(公告)号：US09105646B2

公开(公告)日：2015-08-11

申请号：US13731548

申请日：2012-12-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

Abstract translation: 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

公开(公告)号：US09099430B2

公开(公告)日：2015-08-04

申请号：US14135491

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Xiangxin Rui

IPC: H01L21/02 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L27/10805

Abstract: A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.

Abstract translation: 在形成用于微电子逻辑电路中的去耦电容器中使用基于氧化锆的电介质材料。 在一些实施方案中，掺杂氧化锆基电介质。 在一些实施方案中，掺杂剂包括铝，硅或钇中的至少一种。 在一些实施方案中，基于氧化锆的电介质形成为氧化锆和掺杂剂金属氧化物的纳米氨酸盐。

公开(公告)号：US20150179730A1

公开(公告)日：2015-06-25

申请号：US14135491

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Xiangxin Rui

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L27/10805

Abstract: A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.

Abstract translation: 在形成用于微电子逻辑电路中的去耦电容器中使用基于氧化锆的电介质材料。 在一些实施方案中，掺杂氧化锆基电介质。 在一些实施方案中，掺杂剂包括铝，硅或钇中的至少一种。 在一些实施方案中，基于氧化锆的电介质形成为氧化锆和掺杂剂金属氧化物的纳米氨酸盐。

公开(公告)号：US08980744B2

公开(公告)日：2015-03-17

申请号：US13675852

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L27/108 ,  H01L49/02 ,  C23C16/40

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。