公开(公告)号：US08766346B1

公开(公告)日：2014-07-01

申请号：US13720289

申请日：2012-12-19

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Xiangxin Rui ,  Sergey Barabash

IPC: H01L29/92 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L28/40 ,  H01L28/56 ,  H01L28/60

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor layer inserted between the dielectric layer and at least one of the two electrode layers. In some embodiments, the dielectric layer may be doped with an oxygen donor dopant. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.

Abstract translation: 降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括形成电容器堆叠，该电容器堆叠包括介于介电层和两个电极层中的至少一个之间的供氧体层。 在一些实施例中，介电层可以掺杂有氧供体掺杂剂。 氧供体材料为介电层提供氧气并降低氧空位的浓度，从而减少漏电流。

公开(公告)号：US08846468B2

公开(公告)日：2014-09-30

申请号：US13716375

申请日：2012-12-17

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Xiangxin Rui ,  Sergey Barabash

IPC: H01L21/00 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L28/40 ,  H01L28/56 ,  H01L28/60

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor dopant incorporated within the dielectric layer. The oxygen donor dopants may be incorporated within the dielectric layer during the formation of the dielectric layer. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.

Abstract translation: 用于减少DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括形成包含掺杂在电介质层内的氧供体掺杂剂的电容器堆叠。 在形成电介质层期间，可将氧供体掺杂物掺入电介质层内。 氧供体材料为介电层提供氧气并降低氧空位的浓度，从而减少漏电流。

公开(公告)号：US20140170833A1

公开(公告)日：2014-06-19

申请号：US13716375

申请日：2012-12-17

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

Inventor： Xiangxin Rui ,  Sergey Barabash

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L28/40 ,  H01L28/56 ,  H01L28/60

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor dopant incorporated within the dielectric layer. The oxygen donor dopants may be incorporated within the dielectric layer during the formation of the dielectric layer. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.

Abstract translation: 用于减少DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括形成包含掺杂在电介质层内的氧供体掺杂剂的电容器堆叠。 在形成电介质层期间，可将氧供体掺杂物掺入电介质层内。 氧供体材料为介电层提供氧气并降低氧空位的浓度，从而减少漏电流。

公开(公告)号：US20140167221A1

公开(公告)日：2014-06-19

申请号：US13720289

申请日：2012-12-19

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

Inventor： Xiangxin Rui ,  Sergey Barabash

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L28/40 ,  H01L28/56 ,  H01L28/60

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor layer inserted between the dielectric layer and at least one of the two electrode layers. In some embodiments, the dielectric layer may be doped with an oxygen donor dopant. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.

Abstract translation: 降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括形成电容器堆叠，该电容器堆叠包括介于介电层和两个电极层中的至少一个之间的供氧体层。 在一些实施例中，介电层可以掺杂有氧供体掺杂剂。 氧供体材料为介电层提供氧气并降低氧空位的浓度，从而减少漏电流。

公开(公告)号：US09178011B2

公开(公告)日：2015-11-03

申请号：US14137003

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L49/02 ,  H01L21/28 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

Abstract: A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Abstract translation: 电介质层可以实现类似于具有设置在两个电介质层之间的导电层的基极电介质层的结晶取向。 通过提供具有与基底电介质层相似的晶体结构和晶格参数的导电层，晶体取向可以从基极介电层承载在导电层上，以影响电介质层。 该方法可以用于形成各向异性介电材料的电容器结构，沿着高介电常数的方向。

公开(公告)号：US20150187982A1

公开(公告)日：2015-07-02

申请号：US14141408

申请日：2013-12-26

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Amir Bayati ,  Dipankar Pramanik ,  Zhi-Wen Sun

IPC: H01L31/18

CPC classification number: H01L31/1832 ,  C23C14/0629 ,  C23C16/305 ,  H01L21/02411 ,  H01L21/02422 ,  H01L21/0248 ,  H01L21/02485 ,  H01L21/02499 ,  H01L21/02505 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02631 ,  H01L31/02966 ,  H01L31/0749 ,  H01L31/18 ,  H01L31/1836 ,  Y02E10/541 ,  Y02P70/521

Abstract: Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blende crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT.

Abstract translation: 本文提供的实施方案描述了形成碲化锰 - 碲化物（CMT）的方法，例如用于光伏器件中的方法。 提供了包括具有闪锌矿晶体结构的材料的基板。 CMT形成在衬底之上。 在CMT的形成过程中，维持富阳离子处理条件。 当与常规形成的CMT相比时，所得到的CMT可以更容易地被提供有p型掺杂剂。

公开(公告)号：US08907313B2

公开(公告)日：2014-12-09

申请号：US13719051

申请日：2012-12-18

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

公开(公告)号：US20140264507A1

公开(公告)日：2014-09-18

申请号：US14137866

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Mankoo Lee ,  Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L27/146

CPC classification number: H01L21/76864 ,  H01L21/02005 ,  H01L21/02104 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/14 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14698 ,  H01L29/1606 ,  H01L29/41 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786

Abstract: CMOS imaging sensors having fluorine-passivated structures to reduce dark current are disclosed together with methods of making thereof. The CIS comprises an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors. Methods of preparing a CIS comprise providing a source of fluorine (F) atoms, and annealing in the presence of the source of F atoms. After the annealing, at least one silicon-containing surface or region in the CIS comprises Si—F bonds and is fluorine passivated.

Abstract translation: 公开了具有氟钝化结构以减少暗电流的CMOS成像传感器及其制造方法。 CIS包括衬底上的像素阵列，每个像素包括钉扎光电二极管，与被钉扎光电二极管相邻的隔离沟槽以及多个晶体管。 制备CIS的方法包括提供氟（F）原子源，并在F原子源存在下进行退火。 在退火之后，CIS中的至少一个含硅表面或区域包含Si-F键并被氟钝化。

公开(公告)号：US20140185357A1

公开(公告)日：2014-07-03

申请号：US13728739

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/147 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/1633

Abstract: Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element.

Abstract translation: 适用于存储器件应用的转向元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，操纵元件可以包括第一电极，第二电极和夹在两个电极之间的渐变电介质层。 渐变电介质层可以包括从第一电极到第二电极的不同组成。 带隙的顶部和/或底部的分级能级可以是梯度介电层组成的结果，和/或电极的功函数可以被配置为抑制断开的隧道和热离子电流 和/或最大化导通状态和转向元件断开状态下的隧道和热离子电流的比例。

公开(公告)号：US20140175604A1

公开(公告)日：2014-06-26

申请号：US13725701

申请日：2012-12-21

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

IPC: H01L49/02

CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。