公开(公告)号：US12046511B2

公开(公告)日：2024-07-23

申请号：US17530971

申请日：2021-11-19

Applicant: International Business Machines Corporation

Inventor： Devika Sarkar Grant ,  Somnath Ghosh

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/76885 ,  H01L21/02071 ,  H01L23/53266 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/32135

Abstract: Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

公开(公告)号：US20240014322A1

公开(公告)日：2024-01-11

申请号：US18473482

申请日：2023-09-25

Applicant: International Business Machines Corporation

Inventor： Sung Dae Suk ,  Somnath Ghosh ,  Chen Zhang ,  Junli Wang ,  Devendra K. Sadana ,  Dechao Guo

IPC: H01L29/78 ,  H01L25/07 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L29/7827 ,  H01L25/074 ,  H01L29/0847

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

公开(公告)号：US11682617B2

公开(公告)日：2023-06-20

申请号：US17129971

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Somnath Ghosh ,  Lawrence A. Clevenger ,  Robert Robison

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L21/7682 ,  H01L23/5222

Abstract: An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.

公开(公告)号：US11527434B2

公开(公告)日：2022-12-13

申请号：US16796079

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Daniel James Dechene ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

公开(公告)号：US20220108922A1

公开(公告)日：2022-04-07

申请号：US17551531

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Koichi Motoyama ,  Somnath Ghosh ,  Christopher J. Penny ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

公开(公告)号：US11177160B2

公开(公告)日：2021-11-16

申请号：US16828551

申请日：2020-03-24

Applicant: International Business Machines Corporation

Inventor： Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/033

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a first mandrel layer and a second mandrel layer on the dielectric layer and patterning the first mandrel layer and the second mandrel layer to form respective first and second patterns in the first and second mandrel layers. The first pattern includes a first line segment and a first wing segment. The first wing segment is filled with a first spacer material to form a first spacer. The method further includes removing exposed portions of the first and second mandrel layers, transferring an image of the first and second patterns, patterning the dielectric layer and depositing a metal into the patterned dielectric layer to form a metallic interconnect structure. The metallic interconnect structure includes first and second metallic lines with the second metallic line having a line break corresponding to the first spacer.

公开(公告)号：US20210335666A1

公开(公告)日：2021-10-28

申请号：US16860124

申请日：2020-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chanro Park ,  Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Brent Anderson ,  Somnath Ghosh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213

Abstract: A method is presented for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes. The method includes depositing a dielectric layer over a conductive layer formed over a substrate, forming spacers surrounding mandrel sections formed over the dielectric layer, selectively depositing gap fill material adjacent the spacers, selectively removing the spacers, etching the dielectric layer and the conductive layer to expose a top surface of the substrate, depositing and planarizing an inter-layer dielectric, selectively forming openings in the dielectric layer, and filling the openings with a conductive material to define metal vias.

公开(公告)号：US11158536B2

公开(公告)日：2021-10-26

申请号：US16736478

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Daniel James Dechene ,  Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

公开(公告)号：US20210265166A1

公开(公告)日：2021-08-26

申请号：US16795718

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel James Dechene ,  Somnath Ghosh ,  Hsueh-Chung Chen ,  Carl Radens ,  Lawrence A. Clevenger

IPC: H01L21/033

Abstract: A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

公开(公告)号：US20210143062A1

公开(公告)日：2021-05-13

申请号：US16678053

申请日：2019-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Koichi Motoyama ,  Somnath Ghosh ,  Christopher J. Penny ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.