公开(公告)号：US06504742B1

公开(公告)日：2003-01-07

申请号：US09984934

申请日：2001-10-31

申请人： Lung T. Tran ,  Thomas C. Anthony

发明人： Lung T. Tran ,  Thomas C. Anthony

IPC分类号： G11C502

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C8/12 ,  G11C13/0023 ,  G11C2213/71 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A random access memory (memory) includes one or more planes of memory arrays stacked on top of each other. Each plane may be manufactured separately, and each array within the plane may be enabled/disabled separately. In this manner, each memory array within the plane can be individually tested, and defective memory arrays may be sorted out, which increases the final yield and quality. A memory plane may be stacked on top of each other and on top of an active circuit plane to make a large capacity memory device. The memory may be volatile or non-volatile by using appropriate memory cells as base units. Also, the memory plane may be fabricated separately from the active circuitry. Thus the memory plane does not require a silicon substrate, and may be formed from a glass substrate for example. Further, each memory plane may be individually selected (or enabled) via plane memory select transistors. The array may be individually selected (or enable) via array select transistor. These transistors may be formed from amorphous silicon transistor(s) and/or thin-film transistor(s). The data bus, array select bus, and the plane select bus provide electrical connections between the memory planes and the active circuit plane via side contact pads on each plane. 3-D memory for large storage capacity. The memory may be formed from one or more planes with each plane including one or more memory arrays. Each memory array of each plane may be separately enabled or disabled. The memory array may be formed on silicon or non-silicon based substrate. An active circuit plane may be shared among the memory arrays and planes to perform read and write functions.

摘要翻译： 随机存取存储器（存储器）包括堆叠在彼此之上的一个或多个存储器阵列平面。 每个平面可以单独制造，并且平面内的每个阵列可以单独启用/禁用。 以这种方式，可以单独地测试平面内的每个存储器阵列，并且可以整理出有缺陷的存储器阵列，这增加了最终的产量和质量。 存储器平面可以堆叠在彼此的顶部并且在有源电路平面的顶部上以形成大容量存储器件。 通过使用适当的存储器单元作为基本单元，存储器可以是易失性的或非易失性的。 此外，存储器平面可以与有源电路分开制造。 因此，存储器平面不需要硅衬底，并且可以由例如玻璃衬底形成。 此外，每个存储器平面可以经由平面存储器选择晶体管单独选择（或使能）。 阵列可以通过阵列选择晶体管单独选择（或使能）。 这些晶体管可以由非晶硅晶体管和/或薄膜晶体管形成。 数据总线，阵列选择总线和平面选择总线通过每个平面上的侧接触垫在存储器平面和有源电路平面之间提供电连接。 3-D内存大容量存储。 存储器可以由一个或多个平面形成，每个平面包括一个或多个存储器阵列。 每个平面的每个存储器阵列可以单独启用或禁用。 存储器阵列可以形成在硅或非硅基衬底上。 可以在存储器阵列和平面之间共享有源电路平面以执行读取和写入功能。

公开(公告)号：US06673714B2

公开(公告)日：2004-01-06

申请号：US10133605

申请日：2002-04-25

申请人： Heon Lee ,  Thomas C. Anthony ,  Lung T. Tran

发明人： Heon Lee ,  Thomas C. Anthony ,  Lung T. Tran

IPC分类号： H01L214763

CPC分类号： H01L21/0338 ,  H01L21/0273 ,  H01L21/0337 ,  Y10S438/947

摘要： A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first etch rate is preselected to be faster than the second etch rate when the first and second polymer layers are isotropically etched. The second polymer layer is made from a photo active material and is operative as an etch mask for the first photoresist layer. The etching is continued until the first polymer layer has a sub-lithographic feature size that is less than a lithography limit of a lithography system. A dielectric material is deposited on the etch mask and the first polymer layer. The first polymer layer is lifted-off to define a sub-lithographic sized via.

摘要翻译： 公开了一种制造亚光刻尺寸的通孔的方法。 使用双聚合物方法形成聚合物材料的堆叠层，其中第一聚合物层具有第一蚀刻速率，第二聚合物层具有第二蚀刻速率。 当第一和第二聚合物层被各向同性蚀刻时，预先选择第一蚀刻速率快于第二蚀刻速率。 第二聚合物层由光活性材料制成，并且可用作第一光致抗蚀剂层的蚀刻掩模。 继续蚀刻直到第一聚合物层具有小于光刻系统的光刻极限的亚光刻特征尺寸。 介电材料沉积在蚀刻掩模和第一聚合物层上。 第一聚合物层被剥离以确定亚光刻尺寸的通孔。

公开(公告)号：US06584029B2

公开(公告)日：2003-06-24

申请号：US09924577

申请日：2001-08-09

申请人： Lung T. Tran ,  Thomas C. Anthony ,  Frederick A. Perner

发明人： Lung T. Tran ,  Thomas C. Anthony ,  Frederick A. Perner

IPC分类号： G11C700

CPC分类号： H01L23/5252 ,  G11C13/0004 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programmable (“OTP”) memory includes one or more memory arrays stacked on top of each other. The OTP memory array is a cross-point array where unit memory cells are formed at the cross-points. The unit memory cell may include a fuse and an anti-fuse in series with each other or may include a vertically oriented fuse. Programming the memory may include the steps of selecting unit memory cells, applying a writing voltage such that critical voltage drop across the selected cells occur. This causes the anti-fuse of the cell to break down to a low resistance. The low resistance of the anti-fuse causes a high current pulse to be delivered to the fuse, which in turn melts the fuse to an open state. Reading the memory may include the steps of selecting unit memory cells for reading, applying a reading voltage to the selected memory cells and measuring whether current is present or not. Equipotential sensing may be used to read the memory.

摘要翻译： 一次性可编程（“OTP”）存储器包括堆叠在彼此之上的一个或多个存储器阵列。 OTP存储器阵列是在交叉点处形成单位存储单元的交叉点阵列。 单元存储单元可以包括彼此串联的保险丝和反熔丝，或者可以包括垂直定向的保险丝。 对存储器进行编程可以包括选择单元存储器单元，施加写入电压以使得跨所选单元格出现临界电压降的步骤。 这使得电池的反熔丝分解成低电阻。 反熔丝的低电阻导致高电流脉冲被输送到保险丝，熔丝将熔丝熔化成打开状态。 读取存储器可以包括以下步骤：选择用于读取的单元存储单元，向所选存储单元施加读取电压并测量是否存在电流。 等电位感测可用于读取存储器。

公开(公告)号：US06567301B2

公开(公告)日：2003-05-20

申请号：US09924500

申请日：2001-08-09

申请人： Thomas C. Anthony ,  Lung T. Tran

发明人： Thomas C. Anthony ,  Lung T. Tran

IPC分类号： G11C1136

CPC分类号： G11C17/16

摘要： A one-time programmable unit memory cell includes a vertically oriented fuse and an diode in series. Within the vertically oriented fuse, the current flow is substantially vertical, i.e. perpendicular to the plane of the substrate. Also, the vertically oriented fuse is placed between top and bottom conductors. This vertical placement of the elements helps to increase density of memory devices built using these unit cells. Also, vertically oriented fuses consume very little lateral area, which helps the density even further. The unit memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite because the vertically oriented fuse is left intact. In the written state, the resistance is infinite because the fuse is blown open. The cell may be programmed by applying a critical voltage across the cell enough to cause the fuse to become open. The states are detected by applying a read voltage across the memory cell. If the is not programmed, then a measurable amount flows. Otherwise, no current flows due to the open circuit. A cross-point memory array may be formed with unit memory cells formed at each cross point. With addition of read and write circuitry, the memory array maybe used as memory. However, multiple arrays may be stacked to form high density memory devices.

摘要翻译： 一次性可编程单元存储单元包括垂直取向的熔丝和串联的二极管。 在垂直取向的熔丝内，电流大致垂直于垂直于衬底的平面。 此外，垂直定向的熔断器放置在顶部和底部导体之间。 元件的这种垂直放置有助于增加使用这些单元电池构建的存储器件的密度。 此外，垂直取向的保险丝消耗的横向面积很小，这进一步有助于密度。 单位存储单元具有两种状态，初始状态和写入（编程）状态。 在初始状态下，电池的电阻是有限的，因为垂直取向的保险丝保持原样。 在写入状态下，电阻是无限大的，因为保险丝熔断了。 可以通过在电池上施加足够的临界电压以使熔丝变得开放来对单元进行编程。 通过在存储器单元上施加读取电压来检测状态。 如果没有编程，那么可测量的流量。 否则，由于开路，电流不流动。 交叉点存储器阵列可以形成在每个交叉点处形成的单位存储单元。 通过添加读写电路，存储器阵列可以用作存储器。 然而，可以堆叠多个阵列以形成高密度存储器件。

公开(公告)号：US06205051B1

公开(公告)日：2001-03-20

申请号：US09522269

申请日：2000-03-09

申请人： James A. Brug ,  Thomas C. Anthony ,  Manoj K. Bhattarcharyya

发明人： James A. Brug ,  Thomas C. Anthony ,  Manoj K. Bhattarcharyya

IPC分类号： G11C1114

CPC分类号： G11C11/16 ,  G11C11/14

摘要： A stabilized magnetic memory cell including a data storage layer having an interior region and a pair of end regions near a pair of opposing edges of the data storage layer and a stabilizing material that pins a magnetization in the end regions to a predetermined direction. A method for stabilizing a magnetic memory cell includes the steps of applying a magnetic field that rotates a magnetization in a pair of opposing side regions of a data storage layer of the magnetic memory cell toward a predetermined direction and that reduces free poles in a pair of opposing end regions of the magnetic memory cell, thereby reducing the likelihood of unpredictable switching behavior in the end regions.

摘要翻译： 一种稳定磁存储单元，包括具有在数据存储层的一对相对边缘附近的内部区域和一对端部区域的数据存储层，以及稳定材料，其将端部区域中的磁化引导至预定方向。 一种用于稳定磁存储单元的方法包括以下步骤：施加磁场，该磁场将磁存储单元的数据存储层的一对相对侧区域的磁化旋转到预定方向，并且减小一对 磁存储单元的相对的端部区域，从而降低端部区域中不可预测的开关行为的可能性。

公开(公告)号：US07557782B2

公开(公告)日：2009-07-07

申请号：US10969085

申请日：2004-10-20

申请人： Thomas C. Anthony ,  Lung T. Tran ,  Gary Alfred Gibson

发明人： Thomas C. Anthony ,  Lung T. Tran ,  Gary Alfred Gibson

IPC分类号： G09G3/32

CPC分类号： G09G3/3233 ,  G09G3/2011 ,  G09G3/3216 ,  G09G3/3283 ,  G09G2300/06 ,  G09G2300/0809 ,  G09G2300/0885 ,  G09G2310/0205 ,  G09G2310/0262

摘要： A display element includes a variable optical element that changes appearance in response to changes in current, and a programmable resistance in series with the variable optical element. The resistance of the programmable resistance decreases in response to a first current in a first direction. The resistance of the programmable resistance increases in response to a second current in a second direction.

摘要翻译： 显示元件包括响应于电流变化而改变外观的可变光学元件和与可变光学元件串联的可编程电阻。 可编程电阻的电阻响应于第一方向上的第一电流而减小。 可编程电阻的电阻响应于第二方向上的第二电流而增加。

公开(公告)号：US07027319B2

公开(公告)日：2006-04-11

申请号：US10465714

申请日：2003-06-19

申请人： Thomas C. Anthony ,  Richard L. Hilton ,  Lung T. Tran

发明人： Thomas C. Anthony ,  Richard L. Hilton ,  Lung T. Tran

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： Methods and apparatuses are disclosed for retrieving data stored in a magnetic integrated memory. In one embodiment, the method includes applying a perturbing hard-axis magnetic field to a magnetic element in a magnetic integrated memory and detecting a change in an electrical parameter caused by said perturbing hard-axis magnetic field.

摘要翻译： 公开了用于检索存储在磁性集成存储器中的数据的方法和装置。 在一个实施例中，该方法包括将扰动的硬轴磁场施加到磁性集成存储器中的磁性元件，并检测由所述扰动的硬轴磁场引起的电参数的变化。

公开(公告)号：US06473337B1

公开(公告)日：2002-10-29

申请号：US09983404

申请日：2001-10-24

申请人： Lung T. Tran ,  Manish Sharma ,  Thomas C. Anthony

发明人： Lung T. Tran ,  Manish Sharma ,  Thomas C. Anthony

IPC分类号： G11C1115

CPC分类号： H01L27/222 ,  G11C11/15

摘要： A memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can be changed from a first resistance state to a second resistance state during a write operation. The magnetic tunnel junction can have a differing resistance-voltage characteristic than the tunnel junction, and the differing resistance-voltage characteristics allow the magnetic tunnel junction to be blown without blowing the tunnel junction during a write operation. The change in resistance state of the magnetic tunnel junction changes the resistance of the selected memory cell, which is detectable during a read operation.

摘要翻译： 存储器件包括双隧道结存储器单元，其具有与隧道结串联的磁性隧道结。 在写入操作期间，磁性隧道结可以从第一电阻状态改变到第二电阻状态。 磁性隧道结可以具有与隧道结不同的电阻 - 电压特性，并且不同的电阻 - 电压特性允许磁性隧道结在写入操作期间不会吹动隧道结而被吹动。 磁性隧道结的电阻状态的改变改变了所选择的存储单元的电阻，这在读取操作期间是可检测的。

公开(公告)号：US6072717A

公开(公告)日：2000-06-06

申请号：US146819

申请日：1998-09-04

申请人： James A. Brug ,  Thomas C. Anthony ,  Manoj K. Bhattarcharyya

发明人： James A. Brug ,  Thomas C. Anthony ,  Manoj K. Bhattarcharyya

IPC分类号： G11C11/14 ,  G11C11/16

CPC分类号： G11C11/16 ,  G11C11/14

摘要： A stabilized magnetic memory cell including a data storage layer having an interior region and a pair of end regions near a pair of opposing edges of the data storage layer and a stabilizing material that pins a magnetization in the end regions to a predetermined direction. A method for stabilizing a magnetic memory cell includes the steps of applying a magnetic field that rotates a magnetization in a pair of opposing side regions of a data storage layer of the magnetic memory cell toward a predetermined direction and that reduces free poles in a pair of opposing end regions of the magnetic memory cell, thereby reducing the likelihood of unpredictable switching behavior in the end regions.

摘要翻译： 一种稳定磁存储单元，包括具有在数据存储层的一对相对边缘附近的内部区域和一对端部区域的数据存储层，以及稳定材料，其将端部区域中的磁化引导至预定方向。 一种用于稳定磁存储单元的方法包括以下步骤：施加磁场，该磁场将磁存储单元的数据存储层的一对相对侧区域的磁化旋转到预定方向，并且减小一对 磁存储单元的相对的端部区域，从而降低端部区域中不可预测的开关行为的可能性。

公开(公告)号：US5307226A

公开(公告)日：1994-04-26

申请号：US894415

申请日：1992-06-05

申请人： James A. Brug ,  Thomas C. Anthony ,  Victor W. Hesterman ,  Steven Naberhuis

发明人： James A. Brug ,  Thomas C. Anthony ,  Victor W. Hesterman ,  Steven Naberhuis

IPC分类号： G01D5/245 ,  G01R33/09 ,  G11B5/39 ,  H01L43/08 ,  G11B5/127

CPC分类号： G11B5/3932 ,  G11B5/3903 ,  G11B5/3954

摘要： A magnetoresistive transducer includes at least one magnetoresistive element having a transverse easy axis. The use of a transverse easy axis prevents magnetic domains from forming in the magnetoresistive elements and results in a noise-free device. Various techniques for producing a transverse easy axis include the use of stress, and a magneto strictive material, during the formation of the element to orient the anisotropy of the element transverse to orient the anisotropy of the element transverse to the element, formation of the element in the presence of a magnetic field, high temperature anneal of the element, or any other method of forming the element with a prebiased state.

摘要翻译： 磁阻换能器包括至少一个具有横向容易轴的磁阻元件。 使用横向易轴防止在磁阻元件中形成磁畴，并导致无噪声的装置。 用于产生横向容易轴的各种技术包括在形成元件期间使用应力和磁致伸缩材料，以横向定向元件的各向异性以定向横向于元件的元件的各向异性，元件的形成 在存在磁场的情况下，元件的高温退火，或以预偏置状态形成元件的任何其它方法。