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21.发明授权Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget 有权通过在低热预算下引入氧气和氢气来提高中间间隙金属有效功能的方法公开(公告)号：US09202884B2
公开(公告)日：2015-12-01
申请号：US13100474
申请日：2011-05-04
CPC分类号： H01L29/66545 , H01L21/02244 , H01L21/28088 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.
摘要翻译： 公开了一种用于在金属栅极中用氧形成PMOS晶体管的金属替代栅极的工艺，使得PMOS栅极具有高于4.85的有效功函数。 PMOS栅极中的金属功函数层在低温下被氧化，以将它们的有效功函数增加到期望的PMOS范围。 氢也可以并入在金属栅极和下面的栅极电介质之间的界面处。 公开了用于金属加工功能层的材料和用于低温氧化的方法。
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22.发明授权Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget 有权通过在低热预算下引入氧气和氢气来提高中间间隙金属有效功能的方法公开(公告)号：US07960802B2
公开(公告)日：2011-06-14
申请号：US12621618
申请日：2009-11-19
IPC分类号： H01L29/76
CPC分类号： H01L29/66545 , H01L21/02244 , H01L21/28088 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.
摘要翻译： 公开了一种用于在金属栅极中用氧形成PMOS晶体管的金属替代栅极的工艺，使得PMOS栅极具有高于4.85的有效功函数。 PMOS栅极中的金属功函数层在低温下被氧化，以将它们的有效功函数增加到期望的PMOS范围。 氢也可以并入在金属栅极和下面的栅极电介质之间的界面处。 公开了用于金属加工功能层的材料和用于低温氧化的方法。
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23.发明申请Multiple-gate MOSFET device with lithography independnet silicon body thickness and methods for fabricating the same 审中-公开具有光刻独立硅体厚度的多栅极MOSFET器件及其制造方法公开(公告)号：US20080142890A1
公开(公告)日：2008-06-19
申请号：US12005080
申请日：2007-12-26
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66553 , H01L29/66651 , H01L29/66795 , H01L29/7853 , H01L31/18
摘要： Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are formed along one or more sidewalls of an opening in the form structure. A semiconductor material is deposited in the opening by epitaxial growth or other deposition process, and the form structure and the spacer are removed. A gate structure is then formed along the top and sides of a central portion of the formed semiconductor body. The spacer may be L-shaped, providing an undercut or recess at the bottom of the semiconductor body sidewall, and the gate may be formed in the undercut area to allow fabrication of more than three gates.
摘要翻译： 描述了多栅极MOS晶体管和制造方法，其中晶体管半导体本体的厚度或宽度是光刻独立的，允许具有小于横向栅极长度尺寸的半导体主体的缩放的三栅极和四栅极器件。 在半导体晶片启动结构上提供了一种形式结构，并且在形式结构中的开口的一个或多个侧壁上形成间隔物。 半导体材料通过外延生长或其它沉积工艺沉积在开口中，并且除去形式结构和间隔物。 然后沿着形成的半导体主体的中心部分的顶部和侧面形成栅极结构。 间隔件可以是L形的，在半导体主体侧壁的底部提供底切或凹槽，并且栅极可以形成在底切区域中，以允许制造三个以上的栅极。
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24.发明授权Method of substantially reducing the formation of SiGe abnormal growths on polycrystalline electrodes for strained channel PMOS transistors 有权在应变通道PMOS晶体管的多晶电极上大大减少SiGe异常生长的形成的方法公开(公告)号：US08828825B2
公开(公告)日：2014-09-09
申请号：US13550494
申请日：2012-07-16
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/28035 , H01L21/3211 , H01L21/32139 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.
摘要翻译： 在形成硅锗源极和漏极区域的同时，可能不期望地形成在应变通道PMOS晶体管的栅电极上形成硅锗异常生长的可能性通过使用降低可能性的保护材料而大大减少 在形成硅锗源极和漏极区域期间，栅电极被暴露。
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25.发明申请MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS 有权包括SiON GATE介电的MOS晶体管，在其边界具有增强的氮浓度公开(公告)号：US20120032280A1
公开(公告)日：2012-02-09
申请号：US12850097
申请日：2010-08-04
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/518 , H01L21/28044 , H01L21/28202 , H01L29/78
摘要： A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.
摘要翻译： 形成具有至少一个MOS器件的集成电路（IC）的方法包括在硅表面上形成SiON栅介质层。 在SiON栅极层上沉积栅电极层，然后构图形成栅叠层。 通过图案化揭示了暴露的栅极电介质侧壁。 在暴露的SiON侧壁上形成补充的氧化硅层，然后氮化。 氮化后，后氮化退火（PNA）形成包括N增强SiON侧壁的退火的N增强SiON栅极电介质层，其中沿着恒定厚度的线，N增强SiON侧壁处的N浓度为≥N 大部分退火的N增强SiON栅极层为-2原子％。 形成栅极堆叠的相对侧上的源极和漏极区域以限定栅极叠层下方的沟道区域。
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26.发明授权Multiple-gate MOSFET device with lithography independent silicon body thickness 有权具有光刻独立硅体厚度的多栅极MOSFET器件公开(公告)号：US07489009B2
公开(公告)日：2009-02-10
申请号：US11124942
申请日：2005-05-10
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66553 , H01L29/66651 , H01L29/66795 , H01L29/7853 , H01L31/18
摘要： Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are formed along one or more sidewalls of an opening in the form structure. A semiconductor material is deposited in the opening by epitaxial growth or other deposition process, and the form structure and the spacer are removed. A gate structure is then formed along the top and sides of a central portion of the formed semiconductor body. The spacer may be L-shaped, providing an undercut or recess at the bottom of the semiconductor body sidewall, and the gate may be formed in the undercut area to allow fabrication of more than three gates.
摘要翻译： 描述了多栅极MOS晶体管和制造方法，其中晶体管半导体本体的厚度或宽度是光刻独立的，允许具有小于横向栅极长度尺寸的半导体主体的缩放的三栅极和四栅极器件。 在半导体晶片启动结构上提供了一种形式结构，并且在形式结构中的开口的一个或多个侧壁上形成间隔物。 半导体材料通过外延生长或其它沉积工艺沉积在开口中，并且除去形式结构和间隔物。 然后沿着形成的半导体主体的中心部分的顶部和侧面形成栅极结构。 间隔件可以是L形的，在半导体主体侧壁的底部提供底切或凹槽，并且栅极可以形成在底切区域中，以允许制造三个以上的栅极。
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27.发明授权公开(公告)号：US08643113B2
公开(公告)日：2014-02-04
申请号：US12275812
申请日：2008-11-21
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28185 , H01L21/3221 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L27/11 , H01L29/401 , H01L29/42364 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
摘要翻译： 公开了一种用于在PMOS金属栅中的氧和NMOS栅极中的金属原子富集的NMOS和PMOS晶体管形成金属替代栅极的工艺，使得PMOS栅极具有高于4.85eV的有效功函数，并且NMOS栅极具有以下有效的功函数 4.25 eV。 NMOS和PMOS栅极中的金属功函数层被氧化，以将它们的有效功函数增加到期望的PMOS范围。 在PMOS栅极上形成氧扩散阻挡层，在NMOS栅极上形成氧吸气剂。 吸气剂退火从NMOS功能层提取氧气，并将金属原子富集添加到NMOS功能层，将其有效功函数降低到所需的NMOS范围。 公开了金属加工功能层的工艺和材料，氧化工艺和吸氧剂。
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28.发明申请Method of Substantially Reducing the Formation of SiGe Abnormal Growths on Polycrystalline Electrodes for Strained-Channel PMOS Transistors 有权用于应变通道PMOS晶体管的多结晶电极上SiGe异常生长形成的方法公开(公告)号：US20140017866A1
公开(公告)日：2014-01-16
申请号：US13550494
申请日：2012-07-16
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L29/7848 , H01L21/28035 , H01L21/3211 , H01L21/32139 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.
摘要翻译： 在形成硅锗源极和漏极区域的同时，可能不期望地形成在应变通道PMOS晶体管的栅电极上形成硅锗异常生长的可能性通过使用降低可能性的保护材料而大大减少 在形成硅锗源极和漏极区域期间，栅电极被暴露。
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29.发明申请STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER 有权使用氧气扩散障碍层和极性氧气捕获层的金属栅极氧化浓度控制的结构和方法公开(公告)号：US20100127336A1
公开(公告)日：2010-05-27
申请号：US12275812
申请日：2008-11-21
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28185 , H01L21/3221 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L27/11 , H01L29/401 , H01L29/42364 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
摘要翻译： 公开了一种用于在PMOS金属栅中的氧和NMOS栅极中的金属原子富集的NMOS和PMOS晶体管形成金属替代栅极的工艺，使得PMOS栅极具有高于4.85eV的有效功函数，并且NMOS栅极具有以下有效的功函数 4.25 eV。 NMOS和PMOS栅极中的金属功函数层被氧化，以将它们的有效功函数增加到期望的PMOS范围。 在PMOS栅极上形成氧扩散阻挡层，在NMOS栅极上形成氧吸气剂。 吸气剂退火从NMOS功能层提取氧气，并将金属原子富集添加到NMOS功能层，将其有效功函数降低到所需的NMOS范围。 公开了金属加工功能层的工艺和材料，氧化工艺和吸氧剂。
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30.发明授权Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same 有权具有光刻独立硅体厚度的多栅极MOSFET器件及其制造方法公开(公告)号：US06946377B2
公开(公告)日：2005-09-20
申请号：US10696130
申请日：2003-10-29
IPC分类号： H01L21/3205 , H01L21/336 , H01L27/148 , H01L29/76 , H01L29/786 , H01L31/18
CPC分类号： H01L29/785 , H01L29/66553 , H01L29/66651 , H01L29/66795 , H01L29/7853 , H01L31/18
摘要： Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent, allowing scaled triple and quad-gate devices having semiconductor bodies smaller than a lateral gate length dimension. A form structure is provided over a semiconductor wafer starting structure, and spacers are formed along one or more sidewalls of an opening in the form structure. A semiconductor material is deposited in the opening by epitaxial growth or other deposition process, and the form structure and the spacer are removed. A gate structure is then formed along the top and sides of a central portion of the formed semiconductor body. The spacer may be L-shaped, providing an undercut or recess at the bottom of the semiconductor body sidewall, and the gate may be formed in the undercut area to allow fabrication of more than three gates.
摘要翻译： 描述了多栅极MOS晶体管和制造方法，其中晶体管半导体本体的厚度或宽度是光刻独立的，允许具有小于横向栅极长度尺寸的半导体主体的缩放的三栅极和四栅极器件。 在半导体晶片启动结构上提供了一种形式结构，并且在形式结构中的开口的一个或多个侧壁上形成间隔物。 半导体材料通过外延生长或其它沉积工艺沉积在开口中，并且除去形式结构和间隔物。 然后沿着形成的半导体主体的中心部分的顶部和侧面形成栅极结构。 间隔件可以是L形的，在半导体主体侧壁的底部提供底切或凹槽，并且栅极可以形成在底切区域中，以允许制造三个以上的栅极。
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