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    Method to form a low parasitic capacitance pseudo-SOI CMOS device
    21.
    发明授权
    Method to form a low parasitic capacitance pseudo-SOI CMOS device 有权
    形成低寄生电容伪SOI CMOS器件的方法

    公开(公告)号：US06403485B1

    公开(公告)日：2002-06-11

    申请号：US09846177

    申请日：2001-05-02

    申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    IPC分类号： H01L21302

    CPC分类号： H01L21/76895

    摘要： A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.

    摘要翻译： 描述了一种形成具有可扩展的用于局部互连的源/漏（S / D）区域较高的伪SOI器件的方法。 分离相邻有源区的浅沟槽隔离（STI）区域设置在半导体衬底内。 多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。 在每个栅电极的侧壁上形成电介质间隔物。 沉积覆盖栅电极和衬底的多晶硅层。 在硬掩模层上用抛光光阑抛光多晶硅层。 多晶硅层被回蚀，由此多晶硅层相对于栅电极凹陷。 此后，将多晶硅层蚀刻掉，覆盖STI区域，其中期望相邻的有源区域之间的间隔。 如果在相邻的有源区域之间需要局部互连，则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。 去除硬掩模层。 离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区，以完成具有升高的S / D区的晶体管的形成。

    Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel
    23.
    发明授权
    Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel 失效
    通过首先形成栅/间隔堆叠形成垂直晶体管的方法，然后使用选择性外延形成源极，漏极和沟道

    公开(公告)号：US06544824B1

    公开(公告)日：2003-04-08

    申请号：US10038390

    申请日：2002-01-03

    申请人： Yelehanka Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung

    发明人： Yelehanka Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung

    IPC分类号： H01L2100

    CPC分类号： H01L29/66666

    摘要： A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.

    摘要翻译： 一种垂直晶体管的制造方法。 在衬底中形成掺杂区域。 我们在衬底上依次形成：第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层。 通过第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层形成沟槽。 沟槽有侧壁。 栅极电介质层形成在沟槽的侧壁上。 我们在沟槽中依次形成：第一掺杂层，第一沟道层，第二掺杂层，第三掺杂层，第二沟道层和第四掺杂层。 在该结构上形成盖层。 触点优选地形成于掺杂区域，掺杂层和栅电极。

    METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER
    25.
    发明申请
    METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER 失效
    通过使用介质停止层在门上制造直接接触的方法

    公开(公告)号：US20050059216A1

    公开(公告)日：2005-03-17

    申请号：US10664211

    申请日：2003-09-17

    申请人： Purakh Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    发明人： Purakh Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76802 ,  H01L21/76829

    摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.

    摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（f。）和减小的栅极延迟。

    Method of making direct contact on gate by using dielectric stop layer
    27.
    发明申请
    Method of making direct contact on gate by using dielectric stop layer 有权
    通过使用介电阻挡层在栅极上直接接触的方法

    公开(公告)号：US20050136573A1

    公开(公告)日：2005-06-23

    申请号：US11045958

    申请日：2005-01-28

    申请人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    发明人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76802 ,  H01L21/76829

    摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

    摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

    Method of forming an inductor with continuous metal deposition
    28.
    发明申请
    Method of forming an inductor with continuous metal deposition 审中-公开
    形成具有连续金属沉积的电感器的方法

    公开(公告)号：US20050124131A1

    公开(公告)日：2005-06-09

    申请号：US11034932

    申请日：2005-01-13

    申请人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    发明人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    IPC分类号： H01F17/00 ,  H01L21/02 ,  H01L23/522 ,  H01L21/20 ,  H01L29/00

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

    摘要翻译： 描述了在硅衬底上制造RF电感器件的方法。 沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。 沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。 介电材料的第二层被沉积并图案化以形成通孔/沟槽。 通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。 这些沟槽用铜填充并平坦化。 电介质膜的第三层被沉积并图案化以形成通孔/沟槽。 然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。 这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。

    Process having high tolerance to buried contact mask misalignment by using a PSG spacer
    29.
    发明授权
    Process having high tolerance to buried contact mask misalignment by using a PSG spacer 失效
    通过使用PSG间隔物对掩埋接触掩模未对准具有高耐受性的工艺

    公开(公告)号：US5742088A

    公开(公告)日：1998-04-21

    申请号：US837486

    申请日：1997-04-18

    申请人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

    发明人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

    IPC分类号： H01L21/74 ,  H01L29/08 ,  H01L27/11 ,  H01L29/40

    CPC分类号： H01L21/743

    摘要： A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.

    摘要翻译： 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层，并被蚀刻掉以提供到衬底的开口，其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点，并提供到衬底的开口，其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉，由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层，然后各向同性地蚀刻掉，直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结，其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。

    Process having high tolerance to buried contact mask misalignment by using a PSG spacer
    30.
    发明授权
    Process having high tolerance to buried contact mask misalignment by using a PSG spacer 失效
    通过使用PSG间隔物对掩埋接触掩模未对准具有高耐受性的工艺

    公开(公告)号：US5652152A

    公开(公告)日：1997-07-29

    申请号：US636086

    申请日：1996-04-22

    申请人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

    发明人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

    IPC分类号： H01L21/74 ,  H01L21/441

    CPC分类号： H01L21/743

    摘要： A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.

    摘要翻译： 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层，并被蚀刻掉以提供到衬底的开口，其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点，并提供到衬底的开口，其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉，由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层，然后各向同性地蚀刻掉，直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结，其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。