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21.发明申请Structure and method for scheduler pipeline design for hierarchical link sharing 失效用于分层链路共享的调度器流水线设计的结构和方法公开(公告)号：US20050177644A1
公开(公告)日：2005-08-11
申请号：US10772737
申请日：2004-02-05
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。
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公开(公告)号：US20070294471A1
公开(公告)日：2007-12-20
申请号：US11832220
申请日：2007-08-01
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。
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23.发明申请Method and apparatus for blind checksum and correction for network transmissions 审中-公开用于网络传输的盲校验和校正的方法和装置公开(公告)号：US20060221953A1
公开(公告)日：2006-10-05
申请号：US11097055
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
CPC分类号： H04L69/16 , H04L1/0041 , H04L1/0061 , H04L1/0072 , H04L69/161
摘要： Method and apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.
摘要翻译： 用于在网络传输中提供校验和的方法和装置。 在本发明的一个方面，通过从存储设备检索分组信息来确定要在网络上发送的分组的校验和，所述分组信息将包括在要发送的分组中。 基于检索的分组信息确定盲校验和值，并且基于描述分组的结构的描述符信息将盲校验和值调整为协议校验和。 在分组发送之前，协议校验和被插入到分组中。
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公开(公告)号：US20060187963A1
公开(公告)日：2006-08-24
申请号：US11062036
申请日：2005-02-18
IPC分类号： H04J3/24
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9021
摘要： Methods, computer readable programs and network processor systems appropriate for IP fragmentation and reassembly on network processors comprising a plurality of buffers and buffer control blocks, the buffer control blocks comprising a buffer usage field, the buffer usage field having a value set responsive to a quantity of frame data fragments, wherein the network processor system associates a buffer control block with each buffer and frees a first buffer after reading a frame data fragment responsive to the first buffer control block buffer usage field value indicating only one frame data fragment is present in the first buffer.
摘要翻译： 方法，适用于包括多个缓冲器和缓冲器控制块的网络处理器上的IP分段和重组的计算机可读程序和网络处理器系统，所述缓冲器控制块包括缓冲器使用场，所述缓冲器使用场具有响应于数量的值 其中所述网络处理器系统将缓冲器控制块与每个缓冲器相关联，并且在读取帧数据片段之后释放第一缓冲器，所述第一缓冲器响应于所述第一缓冲器控制块缓冲器使用字段值指示仅存在一个帧数据片段 第一缓冲区。
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公开(公告)号：US20070002172A1
公开(公告)日：2007-01-04
申请号：US11469390
申请日：2006-08-31
申请人： Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
发明人： Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
IPC分类号： H04N11/00
CPC分类号： H04L49/3081 , G06F13/4243 , H04L2012/5681
摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
摘要翻译： 一种通过在控制块中插入限定符来减少存储器访问的方法和系统。 在一个实施例中，系统包括被配置为处理数据帧的处理器。 处理器可以包括多个缓冲器，其被配置为存储数据帧，其中每个数据帧可以与帧控制块相关联。 与数据帧相关联的每个帧控制块可以与一个或多个缓冲器控制块相关联。 每个控制块，例如帧控制块，缓冲器控制块，可以包括包含与当前控制块无关的信息的一个或多个限定符字段。 相反，限定符可以包括与另一个控制块有关的信息。 队列中的最后帧控制块以及与帧控制块相关联的最后一个缓冲器控制块可以包括没有信息的字段，从而减少对这些字段中的访问信息的存储器访问。
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26.发明申请System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置公开(公告)号：US20060101172A1
公开(公告)日：2006-05-11
申请号：US11320277
申请日：2005-12-27
申请人： Claude Basso , Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Marco Heddes , Joseph Logan , Fabrice Verplanken
IPC分类号： G06F5/00
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。
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公开(公告)号：US08681819B2
公开(公告)日：2014-03-25
申请号：US13017963
申请日：2011-01-31
CPC分类号： H04L69/22
摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.
摘要翻译： 一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小） 由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。
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公开(公告)号：US20050259659A1
公开(公告)日：2005-11-24
申请号：US10850296
申请日：2004-05-20
CPC分类号： H04L69/166 , H04L29/06 , H04L69/16
摘要： A method for sequencing delivery of information packets from a router having several processing elements to a receiving processing installation, wherein delivery of the packets must be completed in the order the packets arrive at the router. A linked list of packets is formed in the order they are received at the router, and each packet fragmented into successive fragments. Each fragment is processed at the router. The last fragment of each packet in each linked list is labeled with the sequence in which the packet was received, and enqueued in the order labeled for each last fragment on each linked list. Each fragment of each packet is delivered as processed, except the last fragment of each packet on its linked list to the receiving processor installation, and thereafter, transmitting the final fragment of each packet after processing only if that fragment is at the head of the queue.
摘要翻译： 一种用于将信息分组从具有多个处理元件的路由器传送到接收处理设备的方法，其中分组的传送必须按分组到达路由器的顺序完成。 分组的链表以它们在路由器处接收的顺序形成，并且每个分组被分段成连续的片段。 每个片段在路由器处理。 每个链表中每个数据包的最后一个片段都标有接收数据包的顺序，并按照每个链表上每个最后一个片段标记的顺序排队。 每个分组的每个片段被处理，除了其链接列表上的每个分组的最后片段到接收处理器安装，然后在处理之后仅在该片段位于队列的头部时发送每个分组的最后片段 。
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公开(公告)号：US6144637A
公开(公告)日：2000-11-07
申请号：US991911
申请日：1997-12-16
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译： 描述了用于分组数据通信网络（诸如异步传输模式（ATM））网络的流量整形装置。 该装置包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。 每个传入的数据包被引导到适当的队列。 多个定时电路中的每一个在一系列频率中以不同的频率工作。 选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。
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公开(公告)号：US5724348A
公开(公告)日：1998-03-03
申请号：US858156
申请日：1997-05-05
申请人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
CPC分类号： H04L49/30 , H04L49/104 , H04L49/254 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/5652 , H04L49/3009
摘要： A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.
摘要翻译： 使用多端口数据交换元件描述数据交换机，一个或多个输入/输出适配器，用于从交换机外部接收用户数据单元，以及将通过交换单元切换的小区发送到交换机外部的网络，以及控制元件 包括一个控制处理器。 为了降低数据交换的复杂性，单个控制处理器用于控制处理器所在的控制元件和输入/输出适配器上的硬件模块的操作。 控制通过控制单元提供，控制单元通常遍历与用户数据单元相同的数据路径，并且至少在数据交换机内通常符合用户数据单元的格式。 控制处理器和硬件模块都能够产生控制单元并将其发送到目标，即控制处理器或硬件模块。
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