公开(公告)号：US07307457B2

公开(公告)日：2007-12-11

申请号：US11278169

申请日：2006-03-31

申请人： George M. Braceras ,  John A. Fifield ,  Harold Pilo

发明人： George M. Braceras ,  John A. Fifield ,  Harold Pilo

IPC分类号： H03K19/096 ,  H03K19/094 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.

摘要翻译： 用于动态逻辑的保持器装置包括静态耦合到动态数据路径的第一保持器路径，第一保持器路径被配置为在其评估期间防止动态数据路径的假放电，以及选择性地耦合到动态数据路径的第二保持器路径 。 第二保持器路径被配置为在其评估之前将动态数据路径保持在标称预充电水平，其中在评估期间第二保持器路径与动态数据路径解耦。

公开(公告)号：US07262987B2

公开(公告)日：2007-08-28

申请号：US10906056

申请日：2005-02-01

申请人： Wagdi W. Abadeer ,  John A. Fifield ,  Harold Pilo

发明人： Wagdi W. Abadeer ,  John A. Fifield ,  Harold Pilo

IPC分类号： G11C11/00

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.

摘要翻译： 具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。 隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

公开(公告)号：US07098083B2

公开(公告)日：2006-08-29

申请号：US10652534

申请日：2003-08-29

申请人： John A. Fifield ,  Russell J. Houghton ,  William R. Tonti

发明人： John A. Fifield ,  Russell J. Houghton ,  William R. Tonti

IPC分类号： H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

摘要翻译： 一种可编程元件，其具有第一二极管，其具有电极和设置在所述基板和所述第一器件的所述电极之间的第一绝缘体，所述第一绝缘体具有给定特性的第一值，以及设置有电极和第二绝缘体的FET 在所述基板和所述第二装置的所述电极之间，所述第二绝缘体具有与所述第一值不同的所述给定特性的第二值。 二极管和FET的电极彼此耦合，并且编程能量源耦合到二极管，以使其在编程时永久地降低电阻率。 二极管的编程状态由FET中的电流表示，该电流由读出锁存器读取。 因此，二极管中的小电阻变化转换为锁存器中的大信号增益/变化。 这允许二极管在较低的电压下被编程。

公开(公告)号：US06631503B2

公开(公告)日：2003-10-07

申请号：US09755860

申请日：2001-01-05

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  John A. Fifield

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  John A. Fifield

IPC分类号： G06F1750

CPC分类号： G06F1/206 ,  H03K2005/00143 ,  Y02D10/16

摘要： The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is received by a programmable table circuit of the timing delay system. The programmable table circuit outputs a binary output corresponding to the received binary output. The timing delay system further includes a temperature dependent timing delay circuit having inputs for receiving the binary output of the programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of the programmable table circuit. The band-gap reference can be a temperature independent band-gap reference voltage having a constant-voltage value or a temperature dependent band-gap reference current having a constant-current value. A method is also provided for varying a characteristic of a timing delay signal in accordance with variations of the on-chip temperature of an integrated circuit chip. The method includes the steps of generating a reference parameter; sensing the on-chip temperature of the integrated circuit chip by utilizing at least the reference parameter; providing the sensed on-chip temperature as a binary reading; using the binary reading for providing a respective binary code indicating a timing delay; and varying the characteristic of the timing delay signal, such as the signal's rise time, in accordance with the binary code.

公开(公告)号：US06621324B2

公开(公告)日：2003-09-16

申请号：US09683808

申请日：2002-02-19

申请人： John A. Fifield ,  William R. Tonti

发明人： John A. Fifield ,  William R. Tonti

IPC分类号： H01H3776

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse structure for improved programming efficiency is disclosed wherein the antifuse structure including a first node providing a first voltage, a plurality of antifuse elements, and a plurality of first switches. The plurality of antifuse elements are commonly connected to the first node. The plurality of first switches are sequentially activated during a program mode to individually apply the first voltage to each antifuse element. The antifuse structure may include a second node to which a second voltage is provided. Each of the plurality of first switches may be coupled between the second node and a corresponding one of the plurality of antifuse elements. The antifuse structure may also include a third node to which a fuse latch is connected. A plurality of second switches may be coupled between the third node and a corresponding one of the plurality antifuse elements. The plurality of second switches may be simultaneously activated during a read mode.

摘要翻译： 公开了一种用于提高编程效率的反熔丝结构，其中反熔丝结构包括提供第一电压的第一节点，多个反熔丝元件和多个第一开关。 多个反熔丝元件通常连接到第一节点。 多个第一开关在编程模式期间被依次启动，以分别对每个反熔丝元件施加第一电压。 反熔丝结构可以包括提供第二电压的第二节点。 多个第一开关中的每一个可以耦合在第二节点和多个反熔丝元件中的对应的一个之间。 反熔丝结构还可以包括连接熔丝闩锁的第三节点。 多个第二开关可以耦合在第三节点和多个反熔丝元件中的对应的一个之间。 多个第二开关可以在读取模式期间同时被激活。

公开(公告)号：US06420925B1

公开(公告)日：2002-07-16

申请号：US09757267

申请日：2001-01-09

申请人： John A. Fifield ,  Erik L. Hedberg ,  Claude L. Bertin ,  Nicholas M. van Heel

发明人： John A. Fifield ,  Erik L. Hedberg ,  Claude L. Bertin ,  Nicholas M. van Heel

IPC分类号： H01H3776

CPC分类号： H03K3/356008 ,  G11C17/18

摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.

摘要翻译： 根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。 优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。 可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。 优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。 通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。 特别地，与现有技术方法相比，所需的晶体管的数量显着下降。

公开(公告)号：US06400202B1

公开(公告)日：2002-06-04

申请号：US09988846

申请日：2001-11-19

申请人： John A. Fifield ,  Nicholas M. van Heel ,  Mark D. Jacunski ,  David E. Chapman ,  David E. Douse

发明人： John A. Fifield ,  Nicholas M. van Heel ,  Mark D. Jacunski ,  David E. Chapman ,  David E. Douse

IPC分类号： G06F104

CPC分类号： G11C7/222 ,  G11C7/04 ,  G11C7/1072 ,  H03K5/133 ,  H03K2005/00065

摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.

摘要翻译： 可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。 电流源FET栅极可编程，预定量的电流。 耦合到电流源PET的开关装置接收具有第一和第二电压电平的输入信号。 当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。 还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。 逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。 此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

公开(公告)号：US06373771B1

公开(公告)日：2002-04-16

申请号：US09765035

申请日：2001-01-17

申请人： John A. Fifield ,  Wayne F. Ellis ,  Nicholas M. van Heel

发明人： John A. Fifield ,  Wayne F. Ellis ,  Nicholas M. van Heel

IPC分类号： G11C700

CPC分类号： G11C29/52 ,  G11C17/16 ,  G11C17/18 ,  G11C19/00 ,  G11C29/006 ,  G11C29/50

摘要： An integrated circuit device that obviates laser programming of a two-state element (e.g., a wire fuse or antifuse) by programming (i.e., changing) the conductive state of the two-state element according to a binary bit of programing data serially scanned in. Thereafter, the device can verify the actual programming of the two-state element by sensing the conducting condition and then serially scanning out the conductive state value of the two-sate element as a binary logic bit). The device provides the functionality of being able to test any on-chip non-memory circuitry that depends on a memory circuit being fully functional and operational while still at the wafer tester and before having to “blow” (i.e., program) any fuses.

摘要翻译： 一种集成电路器件，其通过根据串行扫描的编程数据的二进制位编程（即，改变）两状态元件的导通状态来消除双状态元件（例如，线熔丝或反熔丝）的激光编程 此后，器件可以通过感测导通条件来验证双态元件的实际编程，然后串行扫描两元件的导通状态值作为二进制逻辑位）。 该器件提供了能够测试任何片上非存储器电路的功能，该片上非存储器电路取决于完全功能和可操作的存储器电路，同时仍然在晶片测试器处，并且在必须“吹”（即编程）任何保险丝之前。

公开(公告)号：US06177809B1

公开(公告)日：2001-01-23

申请号：US09322470

申请日：1999-05-28

申请人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

发明人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

IPC分类号： H03K19094

CPC分类号： H03K19/00384 ,  H03K19/0005

摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.

摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。

公开(公告)号：US06177807B1

公开(公告)日：2001-01-23

申请号：US09322465

申请日：1999-05-28

申请人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

发明人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

IPC分类号： G03K1716

CPC分类号： G06F13/4086 ,  H03K5/06 ,  H04L25/0298

摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控​​制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。