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公开(公告)号：US06348827B1
公开(公告)日：2002-02-19
申请号：US09501216
申请日：2000-02-10
IPC分类号： H03H1126
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译： 可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。 电流源FET栅极可编程，预定量的电流。 耦合到电流源FET的开关器件接收具有第一和第二电压电平的输入信号。 当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。 还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。 逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。 此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。
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公开(公告)号：US06400202B1
公开(公告)日：2002-06-04
申请号：US09988846
申请日：2001-11-19
IPC分类号： G06F104
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译： 可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。 电流源FET栅极可编程，预定量的电流。 耦合到电流源PET的开关装置接收具有第一和第二电压电平的输入信号。 当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。 还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。 逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。 此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。
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3.发明申请MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE 有权具有全球和本地信号缓存的多银行随机存取存储器结构，用于改进性能公开(公告)号：US20130315022A1
公开(公告)日：2013-11-28
申请号：US13479448
申请日：2012-05-24
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译： 公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。 具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组 连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲 并且因此是真实的信号。 在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。
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4.发明申请MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERENT TEMPERATURE COEFFICIENTS 有权具有开启和关闭状态的存储器阵列具有不同温度系数的字线电压公开(公告)号：US20140003164A1
公开(公告)日：2014-01-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译： 公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。 为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。 在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。 还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。 还公开了一种操作存储器阵列结构的方法。
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5.发明授权Memory array with on and off-state wordline voltages having different temperature coefficients 有权具有不同温度系数的开状态和截止状态字线电压的存储器阵列公开(公告)号：US08902679B2
公开(公告)日：2014-12-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译： 公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。 为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。 在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。 还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。 还公开了一种操作存储器阵列结构的方法。
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6.发明授权Multi-bank random access memory structure with global and local signal buffering for improved performance 有权具有全局和本地信号缓冲的多存储体随机存取存储器结构，以提高性能公开(公告)号：US08649239B2
公开(公告)日：2014-02-11
申请号：US13479448
申请日：2012-05-24
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译： 公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。 具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组 连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲 并且因此是真实的信号。 在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。
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7.发明授权Pre-charge circuit and method for memory devices with shared sense amplifiers 失效具有共享读出放大器的存储器件的预充电电路和方法公开(公告)号：US06580655B2
公开(公告)日：2003-06-17
申请号：US09941911
申请日：2001-08-29
IPC分类号： G11C800
摘要： A pre-charge circuit for a memory device having a sense amplifier shared between right and left banks of memory cells and a method of pre-charging the shared sense amplifier. The circuit is operated according to the method of the invention such that the sense amplifier is always pre-charged from the side that was previously active. The circuit includes right and left bank isolation transistor pairs connected between the shared sense amplifiers and the right and left banks. The isolation transistor pairs are controlled by a flip flop having a left bank state and a right bank state and complementary left and right outputs that turn off the left isolation transistor pair and turn on the right pair during row operations to the right and vice-versa. The flip-flop is kept in the right bank state after a row operation to the right bank so that the sense amplifier is pre-charged from the right after row operations to the right and the flip-flop is kept in the left bank state after a row operation to the left so that the sense amplifier is pre-charged from the left after row operations to the left.
摘要翻译： 一种用于存储器件的预充电电路，其具有在左和右存储单元组之间共享的读出放大器，以及对共享读出放大器进行预充电的方法。 根据本发明的方法操作该电路，使得读出放大器总是从先前有效的一侧预充电。 该电路包括连接在共享读出放大器与左右两列之间的左右隔离晶体管对。 隔离晶体管对由具有左岸状态和右列状态的触发器控制，并且互补的左和右输出关闭左隔离晶体管对并在右侧的行操作期间将右对导通，反之亦然 。 触发器在对右侧行的行操作之后保持在右侧状态，使得读出放大器从右侧行右侧之后被预充电，并且触发器保持在左侧状态之后 左侧的行操作，使得读出放大器从左行后操作向左预充电。
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公开(公告)号：US07194670B2
公开(公告)日：2007-03-20
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
发明人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。
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9.发明授权Method and structure for enabling a redundancy allocation during a multi-bank operation 失效在多行操作期间实现冗余分配的方法和结构公开(公告)号：US07085180B2
公开(公告)日：2006-08-01
申请号：US10777596
申请日：2004-02-12
CPC分类号： G11C29/4401 , G11C29/40 , G11C29/44 , G11C29/808 , G11C2029/0401 , G11C2029/2602
摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.
摘要翻译： 描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。 该方法包括启用通过/故障位检测来激活给定的存储体的步骤。 通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。 通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。 该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。 当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。
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公开(公告)号：US07221601B2
公开(公告)日：2007-05-22
申请号：US11363678
申请日：2006-02-28
CPC分类号： G11C7/1072 , G11C11/4076 , G11C11/408
摘要： A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.
摘要翻译： 一个SDRAM。 SDRAM包括：至少一个DRAM单元组; 所述SDRAM可操作为由第一时钟频率，第一写入恢复时间和用于预充电到行地址选通的第一时间间隔定义的第一规范; 以及用于对可操作到由第二时钟频率，第二写入恢复时间和第二时间间隔定义的第二规范的SDRAM进行编程的装置，用于对行地址选通进行预充电。
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