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21.发明授权Coarse calibration circuit using variable step sizes to reduce jitter and a dynamic course calibration (DCC) circuit for a 2 GHz VCO 失效使用可变步长的粗校准电路可以减少2 GHz VCO的抖动和动态校准（DCC）电路公开(公告)号：US06661267B2
公开(公告)日：2003-12-09
申请号：US10139931
申请日：2002-05-06
IPC分类号： H03L706
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/099 , H03L7/183 , H03L2207/06
摘要： A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output signal indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO, after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift, and avoid jitter caused by an excessive rate of response to calibration inputs.
摘要翻译： 用于锁相环（PLL）的校准系统包括耦合到压控振荡器（VCO）的输出和参考频率源的相位/频率检测器。 连接电荷泵以接收来自相位/频率检测器的误差信号，并向低通滤波器提供电压。 低通滤波器向VCO和比较器系统提供滤波后的误差信号。 比较器系统提供比较器输出信号，指示误差信号的极性何时超过正极限或负极限。 校准装置在经过时间延迟之后，连续向VCO提供增量校准输入。 因此，PLL中的VCO的频率被连续校正以补偿频率漂移，并且避免由对校准输入的响应过大引起的抖动。
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公开(公告)号：US20130120041A1
公开(公告)日：2013-05-16
申请号：US13295351
申请日：2011-11-14
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/0816
摘要： Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.
摘要翻译： 提供了泄漏容限延迟锁定环（DLL）电路装置以及使用泄漏容限DLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。 实施例包括DLL电路装置，包括：主回路和二次校正电路。 主回路包括相位检测器，误差控制器和压控缓冲器（VCB）。 二次校正电路被配置为产生并向误差控制器提供二次误差延迟信号。 二次校正电路包括多个误差发生器。 响应于检测到来自VCB的输出相位信号的特定边缘，每个误差发生器被配置为产生二次误差延迟信号。 主回路被配置为基于第一误差延迟增加信号，第一误差延迟降低信号和次级误差延迟信号中的至少一个来控制相位调整。
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23.发明授权Structure for out of band signaling enhancement for high speed serial driver 有权用于高速串行驱动程序的带外信令增强的结构公开(公告)号：US08144726B2
公开(公告)日：2012-03-27
申请号：US12154796
申请日：2008-05-27
申请人： Huihao Xu , Joseph Natonio , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Joseph Natonio , James D. Rockrohr , Michael A. Sorna
CPC分类号： G06F13/4295
摘要： A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.
摘要翻译： 为微电子串行驱动器提供了一种设计结构。 串行驱动器可操作以在相邻突发间隔期间的第二间隔期间在突发间隔期间和预定共模电压电平期间发送差分模式信号，该串行驱动器包括至少一个预驱动器和耦合到该输出的驱动器 用于发送差分通信信号的预驱动器。 开关电路可操作以在脉冲串间隔的第一电源电压电平和预定共模电压电平之间切换串行驱动器，其中预定共模电压电平与电源电压条件和温度条件的变化无关。
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24.发明授权System and method for latency reduction in speculative decision feedback equalizers 有权投机决策反馈均衡器延迟降低的系统和方法公开(公告)号：US08126045B2
公开(公告)日：2012-02-28
申请号：US12201487
申请日：2008-08-29
申请人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
发明人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.
摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 通道门复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟门控的，用于在预充电时段期间从读出放大器的输出隔离后续电路。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选定信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。
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25.发明授权公开(公告)号：US07855563B2
公开(公告)日：2010-12-21
申请号：US11766268
申请日：2007-06-21
CPC分类号： G01R31/041 , G01R31/026
摘要： A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.
摘要翻译： 提供了一种用于检测信号传输路径中的故障的系统。 在一个实施例中，系统可以包括可变幅度信号衰减器，其可操作以通过可变地衰减输入信号的信号电压摆幅来修改输入信号。 期望地，只有当从高信号电压电平转换到低信号电压电平d时，输入信号才被衰减，使得较高的高电平到低的信号电压摆幅比较小的高到低信号电压衰减 摇摆。 期望地，可能对输出信号施加迟滞的比较器可以检测参考电压电平与修改的输入信号的交叉。 以这种方式，当比较器没有检测到通过修改的输入信号的参考电压电平的预期交叉时，可以确定在信号传输路径中存在故障。
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26.发明申请公开(公告)号：US20080316930A1
公开(公告)日：2008-12-25
申请号：US11766268
申请日：2007-06-21
IPC分类号： G01R31/08
CPC分类号： G01R31/041 , G01R31/026
摘要： A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.
摘要翻译： 提供了一种用于检测信号传输路径中的故障的系统。 在一个实施例中，系统可以包括可变幅度信号衰减器，其可操作以通过可变地衰减输入信号的信号电压摆幅来修改输入信号。 期望地，只有当从高信号电压电平转换到低信号电压电平d时，输入信号才被衰减，使得较高的高电平到低的信号电压摆幅比较小的高到低的信号电压衰减 摇摆。 期望地，可能对输出信号施加迟滞的比较器可以检测参考电压电平与修改的输入信号的交叉。 以这种方式，当比较器没有检测到通过修改的输入信号的参考电压电平的预期交叉时，可以确定在信号传输路径中存在故障。
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27.发明授权High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion 有权具有自适应接收机均衡和可控发射机预失真的高速多模式接收机公开(公告)号：US07409019B2
公开(公告)日：2008-08-05
申请号：US10711713
申请日：2004-09-30
申请人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： H04L27/08
CPC分类号： H04L25/085 , H03F1/3241 , H04L25/0278 , H04L25/0292 , H04L25/03343 , H04L25/061 , H04L2025/0349 , H04L2025/03566 , H04L2025/03617 , H04L2025/03808
摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.
摘要翻译： 提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。 接收机还可操作以执行自适应均衡以接收由发射机发送的信号。
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28.发明申请Automatic adaptive equalization method for high-speed serial transmission link 失效自动自适应均衡方法用于高速串行传输链路公开(公告)号：US20080137721A1
公开(公告)日：2008-06-12
申请号：US11974967
申请日：2007-10-17
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/03343
摘要： In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.
摘要翻译： 在用于执行通信系统的均衡的方法中，可以将预定信号从发射机单元发送到传输线上的下行信道方向上的接收机单元，例如作为在相应方向上同时沿相反方向转变的一对差分信号 传输线的信号导体。 在接收机单元，可以分析从传输线接收的信号的眼图，以确定均衡信息。 均衡信息可以在传输线上的上行方向上从接收机单元发送到发射机单元，并在发射机单元处接收。 使用接收到的均衡信息，可以调整发送单元的发送特性。
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公开(公告)号：US06466100B2
公开(公告)日：2002-10-15
申请号：US09757107
申请日：2001-01-08
IPC分类号： H03B524
CPC分类号： H03L7/0995 , H03B2201/0291 , H03L7/0891 , H03L7/093
摘要： A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain. The latter configuration requires the voltage controlled oscillator to incorporate a source-coupled differential pair which is driven by a low pass filter capacitor output voltage, and connected to load transistors; a current source and a current mirror for generating a tail current; individual banks of transistors to mirror the load transistor currents; a digital-to-analog converter with control lines outputted there from, the digital-to-analog converter used to increase the amount of current allowed to flow to the transconductor output, the current being digitally increased and decreased corresponding to an amount of current pulled from the current source, and mirroring the current through at least one transistor mirror circuit.
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公开(公告)号：US08674737B1
公开(公告)日：2014-03-18
申请号：US13606940
申请日：2012-09-07
IPC分类号： H03K5/12
CPC分类号： H03K19/00361 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096 , H03K2005/00058
摘要： A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.
摘要翻译： 配置为控制驱动器电路的转换速率的转换速率控制电路包括：时钟延迟模块，其接收半速率时钟信号，并且包括多个延迟单元，所述多个延迟单元被配置为产生多个相应的延迟时钟信号，每个延迟单元具有不同的时间 相互延迟 驱动器模块包括与相应数据单元电通信的多个多路复用器，以接收对应的延迟时钟信号。 复用器被配置为响应于延迟的时钟信号输出相应的全速率数据流。 转换驱动器模块还包括与每个多路复用器电通信的输出级电路，以组合每个全速率数据流并产生控制转换速率的最终逐步驱动信号。
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