公开(公告)号：US20090237103A1

公开(公告)日：2009-09-24

申请号：US12051868

申请日：2008-03-20

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

IPC: G01R31/26 ,  H01L23/00 ,  G06F17/50

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract translation: 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

公开(公告)号：US07531392B2

公开(公告)日：2009-05-12

申请号：US11276366

申请日：2006-02-27

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.

Abstract translation: 本发明涉及绝缘体上半导体（SOI）衬底结构，其包含直接位于绝缘体层上的不同晶体取向的表面半导体区域。 本发明还涉及制造这种SOI衬底结构的方法，通过直接在多取向体半导体衬底上生长绝缘体层，该绝缘体层包括直接位于半导体基底层上的不同晶体取向的表面半导体区域，以及去除半导体基底 从而形成包括直接位于绝缘体层上的不同晶体取向的表面半导体区域的多取向SOI衬底结构。

公开(公告)号：US20080272399A1

公开(公告)日：2008-11-06

申请号：US12172305

申请日：2008-07-14

Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC: H01L31/00

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

公开(公告)号：US08077240B2

公开(公告)日：2011-12-13

申请号：US12107825

申请日：2008-04-23

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

IPC: H04N3/14 ,  H04N5/335 ,  H04N9/64 ,  H01L31/062 ,  H01L31/113

CPC classification number: H04N5/361 ,  H04N5/359

Abstract: The image quality of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

Abstract translation: 来自在全球快门模式下操作的CMOS图像传感器阵列的图像帧的图像质量可以通过将来自浮动排水口的泄漏电流引入的噪声分散或随机化在图像帧的行中来增强。 此外，通过考虑暗像素行或暗像素列中的暗像素的输出中的时间依赖性变化，可以提高图像质量。 此外，还可以测量暗像素的输出中的电压和时间相关的变化，以提供引入到浮动排水管中的电荷的噪声的准确估计。 这样的方法可以单独使用或组合使用以提高图像的质量。

公开(公告)号：US20110193146A1

公开(公告)日：2011-08-11

申请号：US13089234

申请日：2011-04-18

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe

IPC: H01L27/146 ,  H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14643

Abstract: A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.

Abstract translation: 像素传感器结构，制造方法和操作方法。 公开了一种缓冲像素单元，其包括用于防止杂散电荷载流子到达暗电流校正像素单元的阻挡区域。 缓冲像素单元位于暗电流校正像素单元附近，并且缓冲像素单元类似于有源像素单元。 因此，围绕暗电流校正像素单元的环境与有源像素单元周围的环境相似。

公开(公告)号：US07977711B2

公开(公告)日：2011-07-12

申请号：US12172305

申请日：2008-07-14

Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC: H01L27/148 ,  H01L31/062

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract translation: 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

公开(公告)号：US20100245644A1

公开(公告)日：2010-09-30

申请号：US12553457

申请日：2009-09-03

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

IPC: H04N5/335 ,  H01L27/00

CPC classification number: H04N5/37452 ,  H01L27/14609 ,  H04N5/35581 ,  H04N5/3575

Abstract: A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.

Abstract translation: 包括列电路的像素传感器单元，用于制造包括列电路的像素传感器单元的设计结构和用于操作包括列电路的像素传感器单元的方法基于多个参考数据点和信号数据点对的测量 从可变电容的浮动扩散。 通过排除或包括传输栅极晶体管电容以及浮动扩散电容来提供可变电容。 这种可变电容为包括列电路的像素传感器单元提供了可变的动态范围。

公开(公告)号：US20100084690A1

公开(公告)日：2010-04-08

申请号：US12634898

申请日：2009-12-10

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

IPC: H01L27/148 ,  H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

Abstract: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

Abstract translation: 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

公开(公告)号：US07675097B2

公开(公告)日：2010-03-09

申请号：US11565801

申请日：2006-12-01

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

IPC: H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

Abstract translation: 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

公开(公告)号：US20080272400A1

公开(公告)日：2008-11-06

申请号：US12172309

申请日：2008-07-14

Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC: H01L31/00

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract translation: 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。