公开(公告)号：US07339211B2

公开(公告)日：2008-03-04

申请号：US10625277

申请日：2003-07-23

Applicant: Dong-Sauk Kim ,  Ho-Seok Lee ,  Byung-Jun Park ,  Il-Young Kwon ,  Jong-Min Lee ,  Hyeong-Soo Kim ,  Jin-Woong Kim ,  Hyung-Bok Choi ,  Dong-Woo Shin

Inventor： Dong-Sauk Kim ,  Ho-Seok Lee ,  Byung-Jun Park ,  Il-Young Kwon ,  Jong-Min Lee ,  Hyeong-Soo Kim ,  Jin-Woong Kim ,  Hyung-Bok Choi ,  Dong-Woo Shin

IPC: H01L27/148 ,  H01L29/768

CPC classification number: H01L27/10855 ,  H01L27/0207 ,  H01L27/10814

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

Abstract translation: 公开了半导体装置及其制造方法，其能够通过扩大有效的电容器面积来形成下部电极并且通过扩大电容器的足够的电容来防止由倾斜或提升现象引起的较短的下部电极。 本发明的半导体器件包括：以有序的间隔距离设置的多个电容器插头; 以及多个用于电容器的下电极，并且以与电容器插头分别连接的有序分隔距离设置。

公开(公告)号：US10090314B2

公开(公告)日：2018-10-02

申请号：US15612229

申请日：2017-06-02

Applicant: Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

Inventor： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

IPC: H01L27/115 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/544 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

公开(公告)号：US09269946B2

公开(公告)日：2016-02-23

申请号：US13315273

申请日：2011-12-08

Applicant: Jong-Min Lee

Inventor： Jong-Min Lee

IPC: H01M10/42 ,  H01M2/34 ,  H01M2/02 ,  H01M6/42 ,  H01M10/04 ,  H01M10/48

CPC classification number: H01M2/347 ,  H01M2/0217 ,  H01M2/348 ,  H01M6/42 ,  H01M10/0436 ,  H01M10/425 ,  H01M10/4257 ,  H01M10/482 ,  H01M10/486 ,  H01M2010/4278 ,  H01M2200/105 ,  H01M2200/106 ,  H01M2200/108

Abstract: A battery pack includes: a bare cell; a protection circuit module electrically connected to the bare cell; a thermistor configured to sense a temperature of the bare cell and electrically coupled to the protection circuit module, the thermistor having a lead, the lead having a lead end portion adjacent to the protection circuit module, the lead end portion having a first side facing the protection circuit module; and a support between the first side of the lead end portion and the protection circuit module.

Abstract translation: 电池组包括：裸电池; 电连接到所述裸电池的保护电路模块; 热敏电阻，其被配置为感测所述裸电池的温度并电耦合到所述保护电路模块，所述热敏电阻具有引线，所述引线具有与所述保护电路模块相邻的引线端部，所述引线端部具有面向所述保护电路模块的第一侧; 保护电路模块; 以及在前端部分的第一侧和保护电路模块之间的支撑。

公开(公告)号：US08736655B2

公开(公告)日：2014-05-27

申请号：US12729627

申请日：2010-03-23

Applicant: Jong-Min Lee

Inventor： Jong-Min Lee

IPC: B41J2/435 ,  B41J2/47 ,  B41J27/00

CPC classification number: B41J2/471 ,  G03G15/043

Abstract: Disclosed are a light scanning unit and an electrophotographic image forming apparatus including the light scanning unit. The light scanning unit may include a light source emitting a light beam, a beam deflector that deflects and scans the light beam emitted from the light source in a main scanning direction, a scanning optical system forming an image of a first portion of the light beam that is deflected and scanned by the beam deflector on a scanning surface and a beam detection sensor receiving a second portion of the light beam that is deflected and scanned by the beam deflector for generating a synchronization signal. The beam detection sensor may include a light receiving surface for receiving the second portion of the light beam, and at least two output terminals that are arranged outside an area of the light receiving surface within which the incident second portion of the light beam is confined.

Abstract translation: 公开了一种光扫描单元和包括该光扫描单元的电子照相图像形成设备。 光扫描单元可以包括发射光束的光源，在主扫描方向偏转和扫描从光源发射的光束的光束偏转器，形成光束的第一部分的图像的扫描光学系统 其被扫描表面上的光束偏转器偏转和扫描，以及接收由光束偏转器偏转和扫描的光束的第二部分的光束检测传感器，用于产生同步信号。 光束检测传感器可以包括用于接收光束的第二部分的光接收表面，以及布置在光接收表面的区域外的至少两个输出端子，光束的入射第二部分在该区域内被限制。

公开(公告)号：US08633895B2

公开(公告)日：2014-01-21

申请号：US13409680

申请日：2012-03-01

Applicant: Yoon-Suk Choi ,  Gi-Tae Mun ,  Seung-Ho Park ,  Jong-Min Lee

Inventor： Yoon-Suk Choi ,  Gi-Tae Mun ,  Seung-Ho Park ,  Jong-Min Lee

IPC: G06F3/02 ,  G09G5/00

CPC classification number: G06F3/0233 ,  G06F3/04886 ,  H04M2250/70

Abstract: A character input mode of a mobile terminal permits easier viewing of characters being entered on a virtual keyboard. An apparatus and a method permitting detection of misprinted/omitted character when performing a special character input mode An output manager outputs a character input screen including a virtual keyboard region and a character input field region when entering a character input mode, and outputs an auxiliary character input field showing information of currently input data on the virtual keyboard region. A display unit outputs the auxiliary character input field, the character input field, and the virtual keyboard. When an input of the virtual keyboard is detected, the output manager outputs information of data corresponding to an input position on the character input field and the auxiliary character input field. The character input mode preferably includes a mode for inputting at least one of text data, symbol data, and emoticon data.

Abstract translation: 移动终端的字符输入模式允许更容易地查看在虚拟键盘上输入的字符。 一种在执行特殊字符输入模式时允许检测错印/省略字符的装置和方法输入管理器在输入字符输入模式时输出包括虚拟键盘区域和字符输入区域的字符输入屏幕，并输出辅助字符 输入字段显示虚拟键盘区域上的当前输入数据的信息。 显示单元输出辅助字符输入字段，字符输入字段和虚拟键盘。 当检测到虚拟键盘的输入时，输出管理器输出对应于字符输入字段和辅助字符输入字段上的输入位置的数据的信息。 字符输入模式优选地包括用于输入文本数据，符号数据和表情符号数据中的至少一个的模式。

公开(公告)号：US20130141831A1

公开(公告)日：2013-06-06

申请号：US13817299

申请日：2011-06-07

Applicant: Jong-Min Lee ,  Gil-Su Kim ,  Chul-Jin Jang

Inventor： Jong-Min Lee ,  Gil-Su Kim ,  Chul-Jin Jang

IPC: H01H50/02

CPC classification number: H01H50/021 ,  H05K5/0039

Abstract: An electronic relay includes: a housing having an interior space therein and a lateral side and a lower side of which are opened, a board installation part being formed along a periphery of the opened side of the housing; a printed circuit board a periphery of which is inserted into and installed in the board installation part of the housing, for shielding the opened side of the housing and performing a switching function; a lower cover for shielding a lower side of the housing, one side edge of the printed circuit board being fixed to the lower cover; and terminals ends of which are electrically connected to the printed circuit board and opposite ends of which pass through the lower cover to protrude to the outside.

Abstract translation: 电子继电器包括：壳体，其内部具有内部空间，其外侧和下侧开放，沿着壳体的敞开侧的周边形成板安装部; 印刷电路板，其周边插入并安装在壳体的板安装部分中，用于屏蔽壳体的开放侧并执行切换功能; 用于屏蔽壳体的下侧的下盖，印刷电路板的一个侧边缘固定到下盖; 并且其端部端部电连接到印刷电路板，并且其相对端通过下盖突出到外部。

公开(公告)号：US20110150326A1

公开(公告)日：2011-06-23

申请号：US12675546

申请日：2008-04-18

Applicant: Haimoon Jeong ,  Chan-Young Lee ,  Whoi-Yul Kim ,  Jong-Min Lee ,  Ki-Hong Park

Inventor： Haimoon Jeong ,  Chan-Young Lee ,  Whoi-Yul Kim ,  Jong-Min Lee ,  Ki-Hong Park

IPC: G06K9/00

CPC classification number: G01N21/8851 ,  G06T7/0004

Abstract: There is provided a processing method of an inspection system for paint coated film of steel bridge using image processing technique comprising: a paint coated film image storing process that stores in a data base (DB) unit a paint coated film image information of a steel bridge photographed by the inspection system; a paint coated film information loading process that loads paint coated film image information through calling a file containing the paint coated film image information to be inspected which is stored in the DB unit; a scale and rust extracting process that displays a scale part and a rust part on an output unit after detecting the rust part and the scale part by an image processing process of the inspection system for paint coated film and storing a calculated percentage of deteriorated are in the DB unit; and a repainting information calculating process that calculates a time for repainting and provide an optimum method for paint coating by deteriorated image information of paint coated film.

Abstract translation: 提供了一种使用图像处理技术的钢桥涂漆膜检查系统的处理方法，包括：涂漆膜图像存储过程，其在数据库（DB）单元中存储钢桥的涂漆膜图像信息 由检验系统拍照; 通过调用包含存储在DB单元中的要检查的涂漆膜图像信息的文件来加载涂漆膜图像信息的涂漆膜信息加载过程; 通过涂漆膜检查系统的图像处理处理检测到锈部分和刻度部分之后，在输出单元上显示刻度部分和锈部分并存储计算的劣化百分比的刻度和锈蚀提取过程在 DB单元; 以及重新涂布信息计算处理，其计算再涂漆的时间，并通过涂漆膜的劣化图像信息提供涂料涂布的最佳方法。

公开(公告)号：US20100133586A1

公开(公告)日：2010-06-03

申请号：US12463011

申请日：2009-05-08

Applicant: Byoung-Gue MIN ,  Jong-Min Lee ,  Seong-II Kim ,  Kyung-Ho Lee ,  Hyung-Sup Yoon ,  Eun-Soo Nam

Inventor： Byoung-Gue MIN ,  Jong-Min Lee ,  Seong-II Kim ,  Kyung-Ho Lee ,  Hyung-Sup Yoon ,  Eun-Soo Nam

IPC: H01L29/737 ,  H01L21/331

CPC classification number: H01L29/42304 ,  H01L29/41708 ,  H01L29/66318 ,  H01L29/7371

Abstract: Provided are a heterojunction bipolar transistor and a method of forming the same. The method includes forming an emitter electrode on an emitter capping pattern, a base electrode on a base pattern, and a collector electrode on a subcollector pattern, the subcollector pattern, the base pattern, an emitter pattern, and the emitter capping pattern being provided to a substrate; patterning a protection insulation layer and a first dummy pattern covering the emitter electrode, the base electrode, and the collector electrode, to expose the emitter electrode, the base electrode, and the collector electrode; forming a second dummy pattern to electrically separate the emitter electrode, the base electrode, and the collector electrode; forming, on the substrate provided with the second dummy pattern, an emitter electrode interconnection connected to the emitter electrode, a base electrode interconnection connected to the base electrode, and a collector electrode interconnection connected to the collector electrode; and removing the first and second dummy patterns.

Abstract translation: 提供了一种异质结双极晶体管及其形成方法。 该方法包括在发射极盖图案上形成发射电极，在基底图案上形成基极，在子集电极图案上形成集电极，将子集电极图案，基底图案，发射极图案和发射极封盖图案设置在 底物; 图案化保护绝缘层和覆盖发射电极，基极和集电极的第一虚拟图案，以暴露发射极，基极和集电极; 形成第二虚设图形以电分离发射电极，基极和集电极; 在设置有第二虚设图案的基板上形成连接到发射极的发射极电极互连，与基极连接的基极互连和与集电极连接的集电极互连; 以及去除第一和第二虚拟图案。

公开(公告)号：US07666738B2

公开(公告)日：2010-02-23

申请号：US11952767

申请日：2007-12-07

Applicant: Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

Inventor： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

IPC: H01L21/8242

CPC classification number: H01L28/84 ,  H01L21/32155 ,  H01L28/91

Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

Abstract translation: 本发明涉及半导体器件的电容器的制造方法。 该方法包括以下步骤：在预定的第一掺杂浓度抑制掺杂剂中形成掺杂有杂质的第一非晶硅层局部凝聚; 在原位条件下在第一非晶硅层上形成杂质未掺杂的第二非晶硅层; 通过图案化所述第一非晶硅层和所述第二非晶硅层来形成存储节点; 在所述存储节点的表面上形成硅晶粒; 以及将杂质掺杂到存储节点和硅晶粒直到达到第二预定浓度以提供存储节点所需的导电性。

公开(公告)号：US20090305495A1

公开(公告)日：2009-12-10

申请号：US12465013

申请日：2009-05-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。