公开(公告)号：US20110108415A1

公开(公告)日：2011-05-12

申请号：US12938797

申请日：2010-11-03

Applicant: UIHYOUNG LEE ,  Namseog Kim ,  WoonHo Seo ,  Min-Suk Han ,  YoungHyun Ju ,  Ju-il Choi

Inventor： UIHYOUNG LEE ,  Namseog Kim ,  WoonHo Seo ,  Min-Suk Han ,  YoungHyun Ju ,  Ju-il Choi

IPC: C25D17/00

CPC classification number: C25D17/005 ,  C25D17/001 ,  C25D17/008 ,  C25D17/02 ,  C25D21/10

Abstract: An apparatus for electroplating a substrate includes a substrate supporting member that supports the substrate such that a plating surface of the substrate faces upwardly, an anode electrode disposed at an upper part of the substrate supporting member, a power source for applying a voltage to the anode electrode and the substrate, and a plating solution supply member for supplying a plating solution onto the substrate.

Abstract translation: 一种用于电镀衬底的设备包括：衬底支撑构件，其支撑衬底，使得衬底的电镀表面朝上，设置在衬底支撑构件的上部的阳极，用于向阳极施加电压的电源 电极和基板，以及用于将电镀液供给到基板上的电镀液供给部件。

公开(公告)号：US20110086486A1

公开(公告)日：2011-04-14

申请号：US12969977

申请日：2010-12-16

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。