公开(公告)号：US06836849B2

公开(公告)日：2004-12-28

申请号：US09826986

申请日：2001-04-05

申请人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

发明人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

IPC分类号： G06F126

CPC分类号： G06F1/3203

摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.

摘要翻译： 描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。 控制器接收与MP系统内的物理参数对应的传感器数据。 控制器还接收与MP系统对应的服务质量和策略参数。 服务质量参数定义了对客户使用MP系统的承诺。 策略参数对应于MP系统的输入和输出的操作限制。 操作输入限制涉及功率或单个处理器可用性的成本和可用性。 操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。 控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。 然后控制器生成控件并将其应用于各个处理器以实现性能目标。

公开(公告)号：US06529924B1

公开(公告)日：2003-03-04

申请号：US09535525

申请日：2000-03-27

申请人： Kevin John Nowka

发明人： Kevin John Nowka

IPC分类号： G06F700

CPC分类号： G06F7/485 ,  G06F7/49936

摘要： A method for generating shift amount signals for an alignment shifter is disclosed. In a process of adding a first floating-point number and a second floating-point number, wherein the floating-point numbers includes a sign, a mantissa, and an exponent, an alignment shifter is used to provide proper alignment for the floating-point numbers. Residue arithmetics are performed on an exponent of the first floating-point number and an exponent of the second floating-point number to generate a residue shift amount. The residue shift amount is then decoded to obtain shift amount signals that are readable by the alignment shifter.

摘要翻译： 公开了一种用于产生对准移位器的移位量信号的方法。 在添加第一浮点数和第二浮点数的处理中，浮点数包括符号，尾数和指数，使用对准移位器为浮点数提供适当的对齐 数字。 残差算术以第一浮点数的指数和第二浮点数的指数执行，以产生残差移位量。 然后将残留偏移量解码以获得可由对准移位器读取的移位量信号。

公开(公告)号：US06360238B1

公开(公告)日：2002-03-19

申请号：US09270469

申请日：1999-03-15

申请人： Sang Hoo Dhong ,  Kyung Tek Lee ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Kyung Tek Lee ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F501

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49936

摘要： A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.

摘要翻译： 公开了具有集成符号选择器的零/一预测器。 通过检查对浮点处理器内的加法器的两个输入操作数的两个相邻位进行传播，产生和杀死，产生前导零字符串和前导字符串。 前导零字符串为正和，前导字符串为负数。 然后从前导零字符串和前导字符串确定归一化偏移量。 然后分别确定两个输入操作数的和的符号，但与归一化偏移量确定处理同时确定。 然后，利用该符号来选择正和或负的正和归一化移位量。

公开(公告)号：US20090302929A1

公开(公告)日：2009-12-10

申请号：US12511658

申请日：2009-07-29

申请人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： H03K3/01

CPC分类号： G11C5/147 ,  G11C11/412 ,  G11C11/417

摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

公开(公告)号：US06629235B1

公开(公告)日：2003-09-30

申请号：US09564943

申请日：2000-05-05

申请人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

发明人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

IPC分类号： G06F944

CPC分类号： G06F9/30094 ,  G06F9/3842

摘要： A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.

摘要翻译： 公开了一种用于支持多个执行单元的条件码寄存器架构。 主执行单元耦合主状态代码寄存器，使得由主执行单元生成的条件代码被存储在主状态代码寄存器中。 非主执行单元耦合到阴影条件代码寄存器，使得由非主执行单元生成的条件代码被存储在阴影条件代码寄存器中。 耦合到主执行单元和非主执行单元的标签单元，使得只有在标签单元内的相应条目被引用到主执行单元或主条件代码时才能读取主条件代码寄存器内的条目 寄存器。

公开(公告)号：US06221769B1

公开(公告)日：2001-04-24

申请号：US09263031

申请日：1999-03-05

申请人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

发明人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

IPC分类号： H01L2144

CPC分类号： H01L21/486 ,  H01L21/76898 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/00

摘要： A method for providing a through wafer connection to an integrated circuit silicon package. A hole is first created in the silicon package with an inner surface area extending from the bottom surface of the silicon package to the top surface of the silicon package. The hole is created by one of two methods. The first involves mechanical drilling with a diamond bit rotated at a high rate of speed. The second involves ultrasonically milling utilizing a slurry and steel fingers. The inner surface area of the hole is covered with an insulating material to insulate the conductive material which is later deposited and to serve as a diffusion barrier, then a seed material is placed in the hole. Finally, the hole is filled with a conductive material which is utilized to provide large power inputs or signaling connections to the integrated circuit chips.

摘要翻译： 一种用于向集成电路硅封装提供贯穿晶片连接的方法。 首先在硅封装中产生一个孔，其中内表面区域从硅封装的底表面延伸到硅封装的顶表面。 孔由两种方法之一创建。 第一个涉及以高速度旋转的钻石钻头的机械钻孔。 第二个涉及使用浆料和钢指的超声波铣削。 孔的内表面积被绝缘材料覆盖，以使稍后沉积的导电材料绝缘并用作扩散阻挡层，然后种子材料放置在孔中。 最后，孔填充有导电材料，该导电材料用于提供大的功率输入或信号连接到集成电路芯片。

公开(公告)号：US06175852B1

公开(公告)日：2001-01-16

申请号：US09114117

申请日：1998-07-13

申请人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F750

CPC分类号： G06F7/508

摘要： A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.

摘要翻译： 公开了一种高速进位 - 前瞻二进制加法器。 二进制加法器包括多行进位查找电路，半和模块和和/进位模块。 第一进位 - 前瞻电路行包括多个8位组生成电路和多个8位组传播电路。 八位组生成电路中的每一个产生相应位位置的生成信号。 八位组传播电路中的每一个产生相应位位置的传播信号。 半和模块用于产生半和信号。 通过利用半和信号，生成信号和传播信号，和/进位模块产生和信号和进位信号。

公开(公告)号：US6166437A

公开(公告)日：2000-12-26

申请号：US290921

申请日：1999-04-12

申请人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

发明人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

IPC分类号： H01L23/13 ,  H01L23/544 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/544 ,  H01L23/13 ,  H01L2223/54426 ,  H01L2224/10165 ,  H01L2224/81141 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2224/0401

摘要： A silicon wafer is etched to form a first and second series of guidance features. The features of the first series are larger than and surround the features of the second series. The second series is clustered into groups and a hole is formed in the center of each group. The wafer is designed to integrate a silicon package having preformed contacts with a plurality of silicon-based chips. The package and each chip has a series of guidance recesses which correspond to the guidance features of the first and second series, respectively. One chip is placed on top of each group of the second series, and the package is placed on top of the first series. The recesses in the package and chips will precisely align with and slidingly engage the upper ends of the features. Since the features of the first series are larger than those of the second series, there is a clearance between the package and the chips. In the final stage of assembly, the package is restrained from movement and a pin is inserted through each hole in the wafer to force the chips into contact with the contacts on the package. Heat is then applied to fuse solder balls on the chips with the contacts to form a complete and finished assembly.

摘要翻译： 蚀刻硅晶片以形成第一和第二系列的引导特征。 第一系列的特征大于第二系列的特征并且围绕着第二系列的特征。 第二个系列分组成群，在每组的中心形成一个孔。 晶片被设计成将具有预成型触点的硅封装与多个硅基芯片集成。 封装和每个芯片具有一系列引导凹槽，其分别对应于第一和第二系列的引导特征。 一个芯片放置在第二个系列的每个组的顶部，并且包装被放置在第一系列的顶部。 封装和芯片中的凹槽将精确地对准并滑动地接合特征的上端。 由于第一系列的特征大于第二系列的特征，所以封装和芯片之间存在间隙。 在组装的最后阶段，封装被限制移动，并且销穿过晶片中的每个孔，以迫使芯片与封装上的触点接触。 然后施加热量以使具有触头的芯片上的焊球熔合以形成完整和完成的组件。

公开(公告)号：US09076509B2

公开(公告)日：2015-07-07

申请号：US12511666

申请日：2009-07-29

申请人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Ching-Te Kent Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C11/412 ,  G11C11/417

CPC分类号： G11C5/147 ,  G11C11/412 ,  G11C11/417

摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

公开(公告)号：US07876131B2

公开(公告)日：2011-01-25

申请号：US11859351

申请日：2007-09-21

申请人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

发明人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

IPC分类号： H03K19/20 ,  H03K19/094 ,  H01L21/84

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

摘要翻译： 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。