公开(公告)号：US20050102651A1

公开(公告)日：2005-05-12

申请号：US10451993

申请日：2001-03-29

申请人： Jun Ueda

发明人： Jun Ueda

IPC分类号： G05B19/05 ,  G06F9/44

CPC分类号： G05B19/056 ,  G05B2219/13107 ,  Y10S715/967

摘要： A programming tool has selection means for selecting a plurality of function blocks displayed in a library format, storage means for storing the function blocks selected through the selection means in the order as they are selected, and drawing means, as a plurality of function blocks selected through the selection means are confirmed, for drawing and display the confirmed function blocks in the order as they are selected.

摘要翻译： 一种编程工具具有用于选择以库格式显示的多个功能块的选择装置，用于按选择顺序存储通过选择装置选择的功能块的存储装置，以及被选择的多个功能块的绘图装置 通过选择手段被确认，用于按照选择的顺序绘制和显示确认的功能块。

公开(公告)号：US4489340A

公开(公告)日：1984-12-18

申请号：US228935

申请日：1981-01-28

申请人： Jun Ueda ,  Haruo Mori ,  Kazuo Hagimura ,  Hirokazu Tsukada ,  Kotaro Kato

发明人： Jun Ueda ,  Haruo Mori ,  Kazuo Hagimura ,  Hirokazu Tsukada ,  Kotaro Kato

IPC分类号： H01L27/144 ,  H01L31/111 ,  H04Q3/52 ,  H01L29/74

CPC分类号： H01L31/1113 ,  H01L27/1443 ,  H04Q3/521

摘要： A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the second P type diffused region and the second N type diffused region, a second gate electrode formed on the second gate insulating layer at a portion above the first gate electrode, a cathode electrode connected to the first N type diffused region, an anode electrode connected to the first P type diffused region and the second gate electrode and a high resistance region formed immediately beneath the first gate insulating layer and between the first and second N type diffused regions.

摘要翻译： 一种PNPN半导体开关，包括N型半导体衬底，形成在N型衬底的表面上的间隔开的第一和第二P型扩散区域，形成在第二P型扩散区域中的间隔开的第一和第二N型扩散区域，第一 栅极绝缘层，形成在第一和第二N型扩散区域之间的第二P型扩散区域的表面上以覆盖其部分;形成在第一和第二N型扩散区域之间的第一栅极绝缘层上的第一栅电极， 电阻区域，设置在所述第一栅极绝缘层上，所述电阻区域的与所述第一栅极电极相反一侧的一端，覆盖所述第一栅电极和所述电阻区域的第二栅极绝缘层，形成在所述第一栅极绝缘层的表面上的半绝缘层 基板除了第一和第二P型扩散区域之外，覆盖半绝缘层的绝缘层，P栅极电极 与第二P型扩散区域和第二N型扩散区域连接的第二栅电极，形成在第一栅极电极上方的第二栅极绝缘层上的第二栅电极，连接到第一N型扩散区域的阴极电极， 连接到第一P型扩散区域和第二栅电极的阳极电极和形成在第一栅极绝缘层正下方以及第一和第二N型扩散区域之间的高电阻区域。

公开(公告)号：US4382691A

公开(公告)日：1983-05-10

申请号：US169312

申请日：1980-07-16

申请人： Masaharu Shida ,  Akira Torisawa ,  Jun Ueda ,  Masaaki Mandai ,  Katsuhiko Sato

发明人： Masaharu Shida ,  Akira Torisawa ,  Jun Ueda ,  Masaaki Mandai ,  Katsuhiko Sato

IPC分类号： G04C3/00 ,  G04C3/14 ,  H02P8/02 ,  G06F1/04

CPC分类号： G04C3/143

摘要： In an analog electronic watch having a calendar display the power required during change of the calendar display, about 6 hours out of 24, is greater than at other times. In order to effect economy in power consumption, the pulse for driving the watch motor during the time other than the period in which the calendar display is being changed is only sufficient to drive the time indicating means. In case the motor fails to step when such pulse is applied, this is detected by a detecting circuit and a corrective drive pulse is applied to the motor so as to drive it.

摘要翻译： 在具有日历的模拟电子手表中，显示日历显示改变期间所需的功率，大约在24小时内大于其他时间。 为了实现电力消耗的经济性，在日历显示改变之前的时间期间用于驱动手表电机的脉冲仅足以驱动时间指示装置。 如果在施加这样的脉冲的情况下电动机不能步进，则由检测电路检测到，并且将纠正驱动脉冲施加到电动机以驱动它。

公开(公告)号：US08960803B2

公开(公告)日：2015-02-24

申请号：US13372843

申请日：2012-02-14

申请人： Hiroyuki Mita ,  Jun Ueda

发明人： Hiroyuki Mita ,  Jun Ueda

IPC分类号： A47B97/00 ,  B60N2/60 ,  B60N2/22

CPC分类号： B60N2/6009 ,  B60N2/22

摘要： A vehicle seat is provided with an operation portion that protrudes toward a rear seat from an opening formed at an outer shield and that is used to unlock a recliner from the rear seat side and a reinforcement member that is attached to a cushion frame side so as to cover a notch formed near the opening of the outer shield. Engagement hooks that engage with respective engagement holes formed at edges of the notch and a fixing portion that is fixed to a plate provided at the cushion frame side are formed at the reinforcement member.

摘要翻译： 车辆座椅设置有从形成在外护罩处的开口向后座突出并用于从后座侧解锁斜倚器的操作部和附接到缓冲框架侧的加强构件，以便 以覆盖形成在外屏蔽件的开口附近的凹口。 在加强构件上形成有与形成在凹口的边缘处的各个接合孔接合的接合钩和固定到设置在缓冲框架侧的板的固定部。

公开(公告)号：US20090246912A1

公开(公告)日：2009-10-01

申请号：US12415493

申请日：2009-03-31

申请人： Jun Ueda

发明人： Jun Ueda

IPC分类号： H01L21/50

CPC分类号： H01L21/561 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor chips are fixed to one of two opposite surfaces of a leadframe, and the leadframe is electrically connected to each semiconductor chip with wires. After having applied water-soluble masking ink to the other surface of the leadframe, a sealed structure is molded. Then, when the sealed structure is cut with cutting water into individual semiconductor packages, burrs of the mold resin formed on the other surface side of the leadframe are removed by the cutting water while the masking ink on the other surface of the leadframe is dissolved and removed by the cutting water.

摘要翻译： 半导体芯片被固定到引线框架的两个相对表面中的一个，并且引线框架通过电线电连接到每个半导体芯片。 在将水溶性掩蔽油墨施加到引线框架的另一表面之后，模制密封结构。 然后，当密封结构用切割水切割成单独的半导体封装时，通过切割水除去在引线框架的另一表面侧形成的模制树脂的毛刺，同时引线框架的另一个表面上的掩蔽墨水溶解， 由切割水除去。

公开(公告)号：US07340683B2

公开(公告)日：2008-03-04

申请号：US10451993

申请日：2001-03-29

申请人： Jun Ueda

发明人： Jun Ueda

IPC分类号： G06F3/048

CPC分类号： G05B19/056 ,  G05B2219/13107 ,  Y10S715/967

摘要： A programming tool has selection means for selecting a plurality of function blocks displayed in a library format, storage means for storing the function blocks selected through the selection means in the order as they are selected, and drawing means, as a plurality of function blocks selected through the selection means are confirmed, for drawing and display the confirmed function blocks in the order as they are selected.

摘要翻译： 一种编程工具具有用于选择以库格式显示的多个功能块的选择装置，用于按选择顺序存储通过选择装置选择的功能块的存储装置，以及被选择的多个功能块的绘图装置 通过选择手段被确认，用于按照选择的顺序绘制和显示确认的功能块。

公开(公告)号：US20050219254A1

公开(公告)日：2005-10-06

申请号：US10520790

申请日：2003-03-05

申请人： Jun Ueda

发明人： Jun Ueda

IPC分类号： G06T11/60 ,  G06T11/80 ,  G09G5/00

CPC分类号： G06T11/60

摘要： A drawing tool for drawing pattern parts with held attributes is provided. It draws pattern parts, based only on a desired pattern part being selected from a pattern part window, and the pattern part passing, along a route in which the pattern part moves with dragged onto a drawing canvas, through a desired attribute display region of attribute palettes for displaying its attributes given with respect to the pattern part, so that the attribute can be selected and set by the pattern part only passing, along the route in which an attribute of the pattern part drawn on the drawing canvas is dragged and dropped onto the drawing canvas, through the attribute display region for displaying the desired attribute; therefore, drawings can be performed by minimal operation.

摘要翻译： 提供了一种用于绘制具有持有属性的图案部件的绘图工具。 它基于仅从图案部分窗口中选择的期望图案部分绘制图案部分，并且图案部分沿着图案部分通过拖动到绘图画布上移动的路线通过所需属性的属性显示区域 用于显示其相对于图案部分给出的属性的调色板，使得可以通过图案部分选择和设置该属性，仅沿着将在绘图画面上绘制的图案部分的属性拖放到其上的路线被拖放到 绘制画布，通过属性显示区域显示所需属性; 因此，可以通过最小的操作来执行附图。

公开(公告)号：US4244000A

公开(公告)日：1981-01-06

申请号：US96165

申请日：1979-11-20

申请人： Jun Ueda ,  Haruo Mori ,  Kazuo Hagimura ,  Kotaro Kato

发明人： Jun Ueda ,  Haruo Mori ,  Kazuo Hagimura ,  Kotaro Kato

IPC分类号： H01L27/144 ,  H01L29/10 ,  H01L29/74 ,  H01L29/747 ,  H01L29/749 ,  H01L31/111 ,  H03K17/082 ,  H03K17/725

CPC分类号： H01L29/747 ,  H01L27/1443 ,  H01L29/102 ,  H01L29/7408 ,  H01L29/742 ,  H01L31/1113 ,  H03K17/0824 ,  H03K17/725

摘要： A circuit for preventing a dV/dt erroneous operation of a PNPN semiconductor switch is replaced by a capacitance on the surface of a semiconductor substrate, a high resistance gate electrode. In other words, such a circuit is formed on the surface of the substrate by a slight modification of the basic design without decreasing the chip area and without isolating component elements.

摘要翻译： 用于防止PNPN半导体开关的dV / dt错误操作的电路由半导体衬底，高电阻栅电极的表面上的电容代替。 换句话说，这种电路通过对基本设计的轻微修改形成在基板的表面上，而不会减小芯片面积并且不隔离组件元件。