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    System and method to synchronize signals in individual integrated circuit components
    29.
    发明申请
    System and method to synchronize signals in individual integrated circuit components 有权
    在单个集成电路组件中同步信号的系统和方法

    公开(公告)号：US20070247960A1

    公开(公告)日：2007-10-25

    申请号：US11408647

    申请日：2006-04-21

    申请人： Alessandro Minzoni ,  Jonghee Han

    发明人： Alessandro Minzoni ,  Jonghee Han

    IPC分类号： G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4093

    摘要： A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.

    摘要翻译： 由集成电路（IC）组件产生的同步输出信号与用于每​​个单独IC组件的所施加的时钟信号同步。 逐渐改变IC组件中的可变反馈延迟，以改变时钟信号和输出信号之间的相位偏移。 在IC组件中监视时钟和输出信号的相对相位顺序。 响应于检测到时钟和输出信号的相对相位顺序的交换，可变反馈延迟不再改变。 在一些实施例中，IC组件可以是SDRAM组件。

    DUTY CYCLE CORRECTOR
    30.
    发明申请
    DUTY CYCLE CORRECTOR 有权
    占空比校正器

    公开(公告)号：US20070241799A1

    公开(公告)日：2007-10-18

    申请号：US11403453

    申请日：2006-04-13

    申请人： Alessandro Minzoni ,  Jonghee Han

    发明人： Alessandro Minzoni ,  Jonghee Han

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is configured to delay the second signal to provide a third signal. The phase detector is configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal. The compensation circuit is configured to compensate for a mismatch between the first controllable delay and the second controllable delay to provide a fourth signal in response to the first signal and a fifth signal approximately 180 degrees out of phase with the fourth signal in response to the second signal.

    摘要翻译： 占空比校正器包括第一可控延迟，第二可控延迟，相位检测器和补偿电路。 第一可控延迟被配置为延迟第一信号以提供第二信号。 第二可控延迟被配置为延迟第二信号以提供第三信号。 相位检测器被配置为调整第一可控延迟和第二可控延迟以将第三信号锁相到第一信号。 补偿电路被配置为补偿第一可控延迟和第二可控延迟之间的失配，以响应于第一信号提供第四信号，并响应于第二信号与第四信号大致180度异相，响应于第二信号 信号。