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公开(公告)号：US20140104920A1
公开(公告)日：2014-04-17
申请号：US14042819
申请日：2013-10-01
发明人： Kazutaka Ikegami , Keiko Abe , Kumiko Nomura , Hiroki Noguchi , Shinobu Fujita
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C5/025 , G11C11/165 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.
摘要翻译： 根据一个实施例，半导体器件包括处理器芯片和堆叠在处理器芯片上的凸起并包括存储单元单元和存储器逻辑单元的存储器芯片。 凸块布置在存储器逻辑单元上。 地址和数据通过使用凸块的共享凸起在处理器芯片和存储器芯片之间传送。
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公开(公告)号：US11893476B2
公开(公告)日：2024-02-06
申请号：US18052086
申请日：2022-11-02
摘要： According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.
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公开(公告)号：US11777006B2
公开(公告)日：2023-10-03
申请号：US17446441
申请日：2021-08-30
IPC分类号： H01L29/423 , H01L29/788 , H01L21/28 , G06N3/008 , G06N3/08 , H01L29/66 , H10B41/30
CPC分类号： H01L29/42324 , G06N3/008 , G06N3/08 , H01L29/40114 , H01L29/66825 , H01L29/7883 , H10B41/30
摘要： In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating film and the second electrode film.
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公开(公告)号：US11586897B2
公开(公告)日：2023-02-21
申请号：US16291400
申请日：2019-03-04
发明人： Yoshifumi Nishi , Radu Berdan , Takao Marukame , Kumiko Nomura
摘要： According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.
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公开(公告)号：US10891108B2
公开(公告)日：2021-01-12
申请号：US16294980
申请日：2019-03-07
发明人： Takao Marukame , Yoshifumi Nishi , Kumiko Nomura
摘要： A calculation device includes: M coefficient storage units provided corresponding to the M coefficients, each of the M coefficient storage units including a positive-side coefficient and a negative-side coefficient representing a coefficient corresponding to a sign of a difference; M multiplication units provided corresponding to the M input values, each of the M multiplication units calculating a positive-side multiply value obtained by multiplying the positive-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value and a negative-side multiply value obtained by multiplying the negative-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value; and an output unit outputting an value according to a difference between a positive-side sum value obtained by summing the M positive-side multiplication values and a negative-side sum value obtained by summing the M negative-side multiplication values.
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公开(公告)号：US20200302275A1
公开(公告)日：2020-09-24
申请号：US16564344
申请日：2019-09-09
发明人： Kumiko Nomura , Takao Marukame , Yoshifumi Nishi
IPC分类号： G06N3/063 , G06F16/901 , G06N3/04
摘要： According to an embodiment, a neural network apparatus includes cores, routers, a tree path, and a short-cut path. The cores are provided according to leaves in a tree structure, each core serving as a circuit that performs calculation or processing for part of elements of the neural network. The routers are provided according to nodes other than the leaves in the tree structure. The tree path connects the cores and the routers such that data is transferred along the tree structure. The short-cut path connects part of the routers such that data is transferred on a route differing from the tree path. The routers transmit data output from each core to any of the cores serving as a transmission destination on one of routes in the tree path and the short-cut path such that the calculation or the processing is performed according to a structure of the neural network.
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公开(公告)号：US20200034695A1
公开(公告)日：2020-01-30
申请号：US16287008
申请日：2019-02-27
发明人： Takao Marukame , Kumiko Nomura , Yoshifumi Nishi
摘要： According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.
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公开(公告)号：US20200005130A1
公开(公告)日：2020-01-02
申请号：US16291400
申请日：2019-03-04
发明人： Yoshifumi Nishi , Radu Berdan , Takao Marukame , Kumiko Nomura
摘要： According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.
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公开(公告)号：US10236062B2
公开(公告)日：2019-03-19
申请号：US14208132
申请日：2014-03-13
发明人： Kazutaka Ikegami , Shinobu Fujita , Keiko Abe , Kumiko Nomura , Hiroki Noguchi
IPC分类号： G06F12/00 , G11C14/00 , G06F1/3228 , G06F1/3287 , G06F1/3296 , G06F12/0895
摘要： According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.
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公开(公告)号：US09557801B2
公开(公告)日：2017-01-31
申请号：US13772518
申请日：2013-02-21
发明人： Kumiko Nomura , Shinobu Fujita , Keiko Abe , Kazutaka Ikegami , Hiroki Noguchi
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/32 , G06F1/3225 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.
摘要翻译： 根据实施例，高速缓存设备包括高速缓冲存储器，访问控制器和功率控制器。 高速缓冲存储器分别包括与多个方式相关联的多个存储区域。 访问控制器控制对存储区域的访问。 功率控制器单独地控制提供给每个存储器区域的功率，使得提供给在预定时间内未被访问的存储区域的功率是低于使得存储区域能够操作的操作功率的待机功率。 功率控制器控制提供给存储区域的功率，使得对于很可能被访问的存储区域的待机功率具有比不太可能被访问的存储区域的待机功率值更接近操作功率的值 。
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