公开(公告)号：US20240321348A1

公开(公告)日：2024-09-26

申请号：US18675257

申请日：2024-05-28

Applicant: KIOXIA CORPORATION

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

IPC: G11C11/56 ,  G06F12/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G06F12/0246

Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

公开(公告)号：US20230087010A1

公开(公告)日：2023-03-23

申请号：US17695086

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.

公开(公告)号：US20220293204A1

公开(公告)日：2022-09-15

申请号：US17349358

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18

Abstract: According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.

公开(公告)号：US20210294527A1

公开(公告)日：2021-09-23

申请号：US17015893

申请日：2020-09-09

Applicant: Kioxia Corporation

Inventor： Yuta AIBA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA

IPC: G06F3/06 ,  G11C19/08

Abstract: According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

公开(公告)号：US20210089392A1

公开(公告)日：2021-03-25

申请号：US16807220

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA ,  Ryo YAMAKI ,  Osamu TORII ,  Naomi TAKEDA

IPC: G06F11/10 ,  G06F9/30

Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

公开(公告)号：US20210082483A1

公开(公告)日：2021-03-18

申请号：US16809630

申请日：2020-03-05

Applicant: Kioxia Corporation

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA

IPC: G11C11/16 ,  G06F9/30

Abstract: According to one embodiment, a shift register memory includes blocks and a control circuit. The blocks each includes data storing shift strings. Each of the data storing shift strings includes layers. The control circuit performs storing and reading data by shifting one layer of the layers, in a direction along each of the data storing shift strings. The reading includes reading data from a first layer of the layers. The storing includes storing data to a second layer of the layers. The control circuit reads first data stored in one or more third layers of the layers, the one or more third layers being successive from the first layer, determines a shift parameter in accordance with the reading of the first data, and performs the reading using the determined shift parameter.